Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

Abstract: A high voltage transistor may be formed on the basis of CMOS techniques for forming sophisticated SOI devices, wherein a fully depleted channel portion may result in low on-resistance and high breakdown voltage. Thus, an LDMOS-type transistor may be formed on the basis of a fully depleted drift region, thereby providing a high degree of scalability and process compatibility with sophisticated CMOS techniques.

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.