Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: A method and apparatus provides fault isolation in a in a highly interconnected system. A fault isolator uses a virtual topology of the system to autonomically isolate the fault. Failing nodes interconnects are identified and then used to traverse a virtual topology to determine the most suspect components as the cause of the reported failures. A failure indication is propagated to each component connected to a failing node in the virtual topology until the next node in the virtual topology is encountered. In preferred embodiments, the failure indications for each component are tallied together as the topology is traversed for each failing node and/or component. A total count of the number of nodes connected to each component is determined for a denominator. A weighting of the likelihood of fault is then determined by dividing the failure indications by the total count.

Abstract: A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: Embodiments of the invention provide a method for deploying and running an application on a massively parallel computer system, while minimizing the costs associated with latency, bandwidth, and limited memory resources. The executable code of a program may be divided into multiple code fragments and distributed to different compute nodes of a parallel computing system. During program execution, one compute node may fetch code fragments from other compute nodes as necessary.

Abstract: An analytical mechanism for a massively parallel computer system automatically analyzes data retrieved from the system, and identifies nodes which exhibit anomalous behavior in comparison to their immediate neighbors. Preferably, anomalous behavior is determined by comparing call-return stack tracebacks for each node, grouping like nodes together, and identifying neighboring nodes which do not themselves belong to the group. A node, not itself in the group, having a large number of neighbors in the group, is a likely locality of error. The analyzer preferably presents this information to the user by sorting the neighbors according to number of adjoining members of the group.

Abstract: A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction.

Abstract: A data collector for a massively parallel computer system obtains call-return stack traceback data for multiple nodes by retrieving partial call-return stack traceback data from each node, grouping the nodes in subsets according to the partial traceback data, and obtaining further call-return stack traceback data from a representative node or nodes of each subset. Preferably, the partial data is a respective instruction address from each node, nodes having identical instruction address being grouped together in the same subset. Preferably, a single node of each subset is chosen and full stack traceback data is retrieved from the call-return stack within the chosen node.

Abstract: Embodiments of the invention provide a method for deploying and running an application on a massively parallel computer system, while minimizing the costs associated with latency, bandwidth, and limited memory resources. The executable code of a program may be divided into multiple code fragments and distributed to different compute nodes of a parallel computing system. During program execution, one compute node may fetch code fragments from other compute nodes as necessary.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: A method, apparatus and program product are provided for increasing the usable memory capacity of a logic simulation hardware emulator. The present invention performs an additional logic synthesis operation during model build to transform an original logical array within a logic model into a transformed logical array, such that a row within the transformed logical array includes a plurality of merged logical array rows from the original logical array. The invention further modifies read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.

Abstract: Embodiments of the invention provide a technique for improving the efficiency of a molecular modeling simulation. In one embodiment, the simulation may parse a kd-tree representing a receptor atom to identify atoms of the receptor within a specified distance of a target point. The target point may represent the center of a spherical envelope enclosing atoms of a ligand atom. A miss-accumulation vector may be used to accumulate a miss distance representing the minimum distance between a target point and a given node of the kd-tree. Thus, although the search algorithm may only evaluate the distance between the target point and a splitting dimension at each node of the kd-tree, the miss-accumulation vector may be used to account for distances over multiple dimensions.

Abstract: A method and apparatus for configuration of a memory controller in a parallel computer system using an extensible markup language (XML) configuration file. In preferred embodiments an XML file with the operation parameters for the memory controller is stored in a bulk storage and used by the computers service node to create a personality file with binary register data that is transferred to static memory. The binary register data is then used during the boot process of the compute nodes to configure the memory controller.

Abstract: A method and apparatus provides fault isolation in a in a highly interconnected system. A fault isolator uses a virtual topology of the system to autonomically isolate the fault. Failing nodes interconnects are identified and then used to traverse a virtual topology to determine the most suspect components as the cause of the reported failures. A failure indication is propagated to each component connected to a failing node in the virtual topology until the next node in the virtual topology is encountered. In preferred embodiments, the failure indications for each component are tallied together as the topology is traversed for each failing node and/or component. A total count of the number of nodes connected to each component is determined for a denominator. A weighting of the likelihood of fault is then determined by dividing the failure indications by the total count.

Abstract: A data collector for a massively parallel computer system obtains call-return stack traceback data for multiple nodes by retrieving partial call-return stack traceback data from each node, grouping the nodes in subsets according to the partial traceback data, and obtaining further call-return stack traceback data from a representative node or nodes of each subset. Preferably, the partial data is a respective instruction address from each node, nodes having identical instruction address being grouped together in the same subset. Preferably, a single node of each subset is chosen and full stack traceback data is retrieved from the call-return stack within the chosen node.

Abstract: The present invention provides a method, apparatus and program-product for a self-healing, reconfigurable logic emulation system, wherein if a signal wire becomes faulty in an emulation cable during an emulation run, the runtime software can automatically reconfigure the emulator to reroute the data destined for the faulty signal wire across a spare wire. Such a feature enables a user to restart the emulation run without having to recompile the simulation model to account for the hardware fault.

Abstract: An analytical mechanism for a massively parallel computer system automatically analyzes data retrieved from the system, and identifies nodes which exhibit anomalous behavior in comparison to their immediate neighbors. Preferably, anomalous behavior is determined by comparing call-return stack tracebacks for each node, grouping like nodes together, and identifying neighboring nodes which do not themselves belong to the group. A node, not itself in the group, having a large number of neighbors in the group, is a likely locality of error.

Abstract: An apparatus and method is disclosed for reducing power consumption in a computing system by moving pages allocated in real memory portions to other real memory portions. When a real memory portion contains no pages, that memory portion can be put into a Deep Power Down (DPD) state that has lower power consumption than when that memory portion is in normal operation. The computing system can also be aware of power consumption of each real memory portion, and, with such awareness, the invention teaches consolidation of pages from real memory portions having relatively higher power consumption to real memory portions having relatively lower power consumption.

Abstract: A method for transmitting local node function parameters to a remote node for execution of the function on the remote node, wherein the method may be embodied on a computer readable medium. The method includes the steps of placing each of the function parameters on a first stack and associating a representation string with the function parameters, wherein each character in the representation string corresponds to the data type of an individual function parameter on the first stack. The method further includes dereferencing pointer parameters on the first stack, generating a pure value buffer with the function parameters and the dereferenced pointers, and transmitting the pure value buffer to the remote node.

Abstract: The present invention relates to the preparation of encapsulated products containing a solid dosage form prepared with up to 35% of an edible matrix material. The composition may be introduced into the capsule as a powder and the capsule containing the powder mixture may then be heated to melt the matrix. The resulting capsule products exhibit the favorable texture of a capsule in conjunction with the hardness, shelf stability and security of the solid formulation. The composition of the present invention may be prepared and used as a direct tableting granulation as well as the filler or core for the capsule product. A method and corresponding apparatus are likewise disclosed and contemplated herein.