Abstract: A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).

Abstract: A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.

Abstract: A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=Ff?1{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (Pref(t)) to verify whether power consumption within power domain matches expectations.

Abstract: A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).

Abstract: Printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. Multiple collinear slots in the form of a dashed line are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane and improve the strength of the PWB. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots are dashed and may be made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends.

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

Abstract: A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.

Abstract: An apparatus for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends.

Abstract: A method and apparatus for balancing power plane pin currents in a printed wiring board (PWB) uses a set of collinear slots in the form of a dashed line to reduce pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. The slots are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of an electrical signal line that achieves an increased measurement bandwidth, namely a measurement bandwidth >4 GHz. To achieve this the electrical signal line under test has several neighboring signal lines which are connected to ground on one side and left open on the opposite side in an alternating manner.

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract: A method and apparatus for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.

Abstract: A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.