Abstract: A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Abstract: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

Abstract: An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.

Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Abstract: To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.

Abstract: A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Abstract: A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.

Abstract: In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.

Abstract: An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.

Abstract: When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

Abstract: A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.