Patents by Inventor Thomas Mittelholzer

Thomas Mittelholzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ERROR-CORRECTION ENCODING AND DECODING
    Publication number: 20150309875
    Abstract: A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n?, thereby to define a codeword, having n2 code symbols corresponding to respective locations of the array, of a quarter product code defined by CQ={X?XT?(X?XT)F:X?C} where X is an n by n-symbol matrix defining a codeword of the product code, XT is the transpose matrix of X, and (X?XT)F is a reflection of matrix (X?XT) in the anti-diagonal thereof.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 29, 2015
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • ERROR-CORRECTION ENCODING AND DECODING
    Publication number: 20150309869
    Abstract: A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n?, thereby to define a codeword, having n2 code symbols corresponding to respective locations of the array, of a quarter product code defined by CQ={X?XT?(X?XT)F: X?C} where X is an n by n-symbol matrix defining a codeword of the product code, XT is the transpose matrix of X, and (X?XT)F is a reflection of matrix (X?XT) in the anti-diagonal thereof.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 29, 2015
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Combination error and erasure decoding for product codes
    Patent number: 9166627
    Abstract: In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Keisuke Tanaka
  • TAPE HEADER FORMAT HAVING EFFICIENT AND ROBUST CODEWORD INTERLEAVE DESIGNATION (CWID) PROTECTION
    Publication number: 20150261608
    Abstract: In one embodiment, a computer program product for providing header protection in magnetic tape recording includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to: calculate or obtain, by the processor, codeword interleave designation (CWID) parity for all CWIDs in a codeword interleave (CWI) set header, the CWID parity including error correction coding (ECC) parity, and store, by the processor, the CWID parity to a magnetic tape in one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity. Other systems and methods for providing header protection in magnetic tape recording are described in more embodiments.
    Type: Application
    Filed: May 30, 2015
    Publication date: September 17, 2015
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Keisuke Tanaka
  • Generating a code alphabet of symbols to generate codewords for words used with a program
    Patent number: 9106254
    Abstract: Provided are a computer program product, system, and method for generating a code alphabet for use by a deployed program to determine codewords for words. A first code alphabet has a first number of symbols that provide variable length codings of the words. A second code alphabet is generated having a second number of symbols formed by merging the symbols in the first code alphabet, wherein the second code alphabet comprises the code alphabet used by the deployed program.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Glen A. Jaquette, Thomas Mittelholzer
  • Tape header format having efficient and robust codeword interleave designation (CWID) protection
    Patent number: 9064541
    Abstract: In one embodiment, a system for providing header protection in magnetic tape recording is adapted to write a codeword interleave (CWI) set on a magnetic tape including a plurality of CWIs equal to a number of tracks, wherein a data set includes a plurality of CWI sets, provide a CWI set header for the CWI set, the CWI set header including a CWI header for each CWI in the CWI set, each CWI header including at least a CWI Designation (CWID) which indicates a location of the CWI within the data set, calculate or obtain CWID parity for all CWIDs in the CWI set header, the CWID parity including error correction coding (ECC) parity, and store the CWID parity to one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Keisuke Tanaka
  • EXTENSION OF PRODUCT CODES WITH APPLICATIONS TO TAPE AND PARALLEL CHANNELS
    Publication number: 20150169397
    Abstract: An aspect is a method that includes receiving (k0?1)k1+k2 write data symbols, where k2<k1. The write data symbols are arranged in an array that includes k0?1 rows of length k1 followed by a row of length k2. The first k2 columns are encoded to form a partially encoded array using a vertical error correcting code of length m, m>k0, resulting in k2 columns of length m including the write data symbols and vertical parity values. The k0?1 rows of the write data symbols of length k1 and the m?k0+1 rows from the partially encoded array are encoded into an encoded array of m rows of length n columns, n>k1 including at least one parity value in each of the m rows, thereby enabling correction of up to (n?k1)/2 errors in any row and up to (n?k2)/2 errors in up to m?k0+1 rows of the encoded array.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Mario Blaum, Roy D. Cideciyan, Steven R. Hetzler, Thomas Mittelholzer
  • DEVICE FOR SELECTING A LEVEL FOR AT LEAST ONE READ VOLTAGE
    Publication number: 20150169468
    Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Inventors: Charles J. Camp, Evangelos S. Eleftheriou, Thomas Mittelholzer, Thomas Parnell, Nikolaos Papandreou, Charalampos Pozidis, Andrew Walls
  • Encoding a data word for writing the encoded data word in a multi-level solid state memory
    Patent number: 9059744
    Abstract: A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q?d) symbol values, d?[1, . . . , q?1], depending on a state of the N cells.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • OPTIMUM TAPE LAYOUT SELECTION FOR IMPROVED ERROR CORRECTION CAPABILITY
    Publication number: 20150155003
    Abstract: According to one embodiment, a system for selecting an optimum tape layout to store data on a tape medium includes a processor and logic integrated with and/or executable by the processor, the logic being configured to compute a set of all minimum distances corresponding to a plurality of data set layouts, wherein each minimum distance is computed between a location of a first codeword interleave (CWI) and locations of all other CWIs in a common sub data set (SDS), and calculate a first performance metric associated with each possible set of parameters using the set of all minimum distances for the plurality of data set layouts, the parameters being associated with at least a tape drive and the tape medium. More systems, methods, and computer program products for selecting optimum tape layouts to store data on tape media are described in accordance with other embodiments.
    Type: Application
    Filed: February 10, 2015
    Publication date: June 4, 2015
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer
  • Adaptive soft-output detector for magnetic tape read channels
    Patent number: 9047918
    Abstract: In one embodiment, a method includes passing a signal through an adaptive noise whitening filter, wherein one or more noise whitening coefficients used in the noise whitening filter are updated using a noise whitening filter coefficient updater, wherein the noise whitening filter is configured to process the signal according to a transfer polynomial: W(D)=1?(p1D+ . . . +p??D??), where p1 . . . p?? are noise whitening coefficients, where a tape channel is characterized by a transfer polynomial F(D)=1+f1D+ . . . +fLDL where D is delay corresponding to bit duration, with 2L being a number of states of the tape channel, wherein a soft detector has a total of 2L+? states, the noise whitening filter comprises 2?? states, ?? is greater than ?, L represents a memory length of the tape channel, and ? represents a memory length of the noise whitening filter.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Katherine T. Blinick, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE
    Publication number: 20150149860
    Abstract: In one embodiment, a computer program product for iterative read channel operation has program instructions embodied therewith that are executable by a controller to cause the controller to: in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced: execute one or more digital front-end (DFE) functions on a plurality of signal samples employing the set of decisions provided by a decoder; execute a detection algorithm on the signal samples using a detector employing the set of decisions provided by the decoder to regenerate the set of decisions provided by a detector; execute a decoding algorithm of an error correcting code (ECC) using the set of decisions provided by the detector to regenerate the set of decisions provided by the decoder; and output decoding information relating to the signal samples when the decoding algorithm produces a valid codeword.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 28, 2015
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • MULTI-STAGE CODEWORD DETECTOR
    Publication number: 20150149816
    Abstract: A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal.
    Type: Application
    Filed: September 25, 2014
    Publication date: May 28, 2015
    Inventors: Theodore Antonakopoulos, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • DATA ENCODING IN SOLID-STATE STORAGE APPARATUS
    Publication number: 20150149872
    Abstract: A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells.
    Type: Application
    Filed: September 25, 2014
    Publication date: May 28, 2015
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Adaptive soft-output detector for magnetic tape read channels
    Patent number: 9042049
    Abstract: In accordance with one embodiment, a computer program product includes a computer readable storage medium having computer readable program code that is readable and/or executable by a processor to: receive a signal including precoded data read from a magnetic tape medium and pass the signal through a soft detector to calculator first soft information about each bit of the signal and to provide adaptive compensation for the precoded data, send the first soft information to a soft decoder, pass the signal through the soft decoder to calculate second soft information about each bit the signal, and send the second soft information to the soft detector, wherein the precoded data is passed through at least one precoder prior to being written to the magnetic tape medium via a precoder that applies 1/(1?D2) to bits of data, where D is delay corresponding to bit duration
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Katherine T. Blinick, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Adaptive soft-output detector for magnetic tape read channels
    Patent number: 9036287
    Abstract: In one embodiment, a method includes passing a signal through a noise whitening filter, passing the signal through a soft detector to calculate first soft information, passing the signal through the soft decoder to calculate second soft information based on the first soft information, and sending the second soft information to the soft detector, wherein the noise whitening filter is configured to process the signal according to the following transfer polynomial: W(D)=1?(p1D+ . . . p1D?), where p1 . . . p? are noise whitening coefficients, D is delay corresponding to bit duration, and a transfer polynomial of the tape channel is F(D)=1+f1D+ . . . +fLDL, wherein L represents a memory length of the tape channel, and wherein ? represents a memory length of the noise whitening filter. Other methods, systems, and computer program products are described in more embodiments.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Katherine T. Blinick, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Data management in solid state storage systems
    Patent number: 9037951
    Abstract: Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu, Ilias Iliadas, Thomas Mittelholzer
  • ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE HAVING DROPOUT MITIGATION
    Publication number: 20150109698
    Abstract: According to one embodiment, a computer program product for dropout detection in a read channel includes a computer readable storage medium having program code embodied therewith, the embedded program code being readable and/or executable by a processor to execute dropout detection on a block of signal samples to detect one or more dropout events employing a set of decisions provided by a detector executing a detection algorithm, determine an approximate location for each of the one or more detected dropout events, statistically characterize the one or more detected dropout events to calculate one or more dropout profiles, and selectively filter the block of signal samples during a duration of each of the detected dropout events. Other computer program products, systems, and methods for detecting dropouts are presented in more embodiments.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Optimum tape layout selection for improved error correction capability
    Patent number: 9007709
    Abstract: According to one embodiment, a system for selecting an optimum tape layout to store data on a tape medium may include a processor and logic integrated with and/or executable by the processor, the logic being configured to: select a family of data set layouts based on parameters associated with at least a tape drive and the tape medium, compute a set of all minimum distances for the selected family of data set layouts, calculate a first performance metric associated with each possible set of parameters, select a best first performance metric from all calculated first performance metrics and store a set of parameters associated with the best first performance metric, and select a data set layout algorithm which utilizes the set of parameters associated with the best first performance metric, wherein the data set layout algorithm and a rewrite layout algorithm combine to form an optimum tape layout.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer
  • TAPE HEADER PROTECTION SCHEME FOR USE IN A TAPE STORAGE SUBSYSTEM
    Publication number: 20150085393
    Abstract: In one embodiment, a system for integrating data and header protection includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive a data array organized in rows and columns, each row of the data array comprising two or more interleaved C1 codewords (CWI), and modify one or more rows of the data array to include a header and error correction code (ECC) parity to form one or more modified rows, wherein each modified row includes two or more interleaved codewords, at least one codeword being a C1? codeword which includes ECC parity, wherein each header comprises a CWI Designation (CWID) which indicates a location of the CWI within the data array, and wherein none of the CWIDs are split across multiple C1? codewords in a single modified row. Other systems, methods, and computer program products are presented in additional embodiments.
    Type: Application
    Filed: December 2, 2014
    Publication date: March 26, 2015
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Keisuke Tanaka