Abstract: A semiconductor memory device includes a ferroelectric memory having a non-volatile operation mode and a volatile operation mode; an input terminal to which an input signal indicating a voltage level of a power source voltage is input; a first signal generating circuit outputting a first control signal for regulating activation and inactivation of the non-volatile operation mode to the ferroelectric memory; and a second signal generating circuit outputting a second control signal for regulating the activation and inactivation of the non-volatile operation mode to the first signal generating circuit, based on the input signal. The non-volatile operation mode and the volatile operation mode are automatically switched with each other in accordance with changes in the voltage level of the power source voltage under a first operation condition, and only the volatile operation mode is activated under a second operation condition.

Abstract: A reference scheme for a Dynamic Shadow Random Access Memory which provides a reference voltage circuit used for determining the data state of a ferroelectric memory cell operating in either dynamic (DRAM) or nonvolatile (NVRAM) modes. The reference voltage circuit includes two ferroelectric capacitors with associated data state setting transistors such that in either DRAM or NVRAM operating mode, the two capacitors store opposite data states. The circuit also includes means for alternating the data state of each capacitor. In operation, the ferroelectric capacitors are discharged to associated bitlines producing voltages which are averaged to derive a half-state reference voltage level. The reference voltage is used to determine the state of an associated memory cell. Additionally, a ferroelectric memory circuit is provided which includes an array of reference voltage circuits configured and operated in a manner to reduce the fatigue and imprinting experienced by the reference capacitors.

Abstract: A semiconductor memory device includes: a plurality of bit lines disposed on a substrate; a plurality of word lines and a plurality of data lines disposed on the substrate in a direction crossing with the bit lines; a plurality of memory cells disposed in a matrix at portions corresponding to respective crossing points of the bit lines and the word lines, each of the plurality of memory cells having at least one switching transistor and at least one ferroelectric capacitor including a ferroelectric film as an insulating film to form a non-volatile ferroelectric memory storing information by a polarization direction of the ferroelectric film; a substrate voltage generating circuit which supplies a negative substrate voltage to the substrate; and a power-on reset circuit which output and applies a predetermined positive voltage to the word lines during a time period from a power-on until the substrate voltage is stabilized.