Patents by Inventor Thomas Mountsier
Thomas Mountsier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9618846Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.Type: GrantFiled: February 25, 2016Date of Patent: April 11, 2017Assignee: Lam Research CorporationInventors: Nader Shamma, Thomas Mountsier, Donald Schlosser
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Publication number: 20160179005Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.Type: ApplicationFiled: February 25, 2016Publication date: June 23, 2016Inventors: Nader Shamma, Thomas Mountsier, Donald Schlosser
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Patent number: 9304396Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.Type: GrantFiled: February 20, 2014Date of Patent: April 5, 2016Assignee: Lam Research CorporationInventors: Nader Shamma, Thomas Mountsier, Don Schlosser
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Publication number: 20140239462Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.Type: ApplicationFiled: February 20, 2014Publication date: August 28, 2014Inventors: Nader Shamma, Thomas Mountsier, Donald Schlosser
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Patent number: 8298936Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.Type: GrantFiled: February 3, 2010Date of Patent: October 30, 2012Assignee: Novellus Systems, Inc.Inventors: Robert Rozbicki, Bart van Schravendijk, Thomas Mountsier, Wen Wu
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Patent number: 7531463Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.Type: GrantFiled: October 24, 2006Date of Patent: May 12, 2009Assignee: Novellus Systems, Inc.Inventors: Daniel A. Koos, Steven T. Mayer, Heung L. Park, Timothy Patrick Cleary, Thomas Mountsier
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Patent number: 7338908Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.Type: GrantFiled: October 20, 2003Date of Patent: March 4, 2008Assignee: Novellus Systems, Inc.Inventors: Daniel A. Koos, Steven T. Mayer, Heung L. Park, Timothy Patrick Cleary, Thomas Mountsier
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Publication number: 20070105377Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.Type: ApplicationFiled: October 24, 2006Publication date: May 10, 2007Inventors: Daniel Koos, Steven Mayer, Heung Park, Timothy Cleary, Thomas Mountsier
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Patent number: 6613199Abstract: A hollow cathode magnetron comprises an open top target within a hollow cathode. The open top target can be biased to a negative potential so as to form an electric field within the cathode to generate a plasma. The magnetron uses at least one electromagnetic coil to shape and maintain a density of the plasma within the cathode. The magnetron also has an anode located beneath the cathode. The open top target can have one of several different geometries including flat annular, conical and cylindrical, etc.Type: GrantFiled: October 25, 2001Date of Patent: September 2, 2003Assignee: Novellus Systems, Inc.Inventors: Jeffrey A. Tobin, Jean Qing Lu, Thomas Mountsier, Hong Mei Zhang
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Patent number: 5810933Abstract: A wafer cooling device (WCD) for cooling a substrate, such as a wafer, during processing is presented. The substrate is mounted to an WCD heat transfer surface, thereby forming a cavity in between the substrate and the heat transfer surface into which gas is incorporated. An array of protuberances within the cavity provide support for the wafer. Contact heat conduction between the substrate and WCD is reduced by reducing the amount of direct contact between the substrate and WCD. Thus the heat transfer coefficient from the substrate, and hence substrate temperature, is controlled by adjusting the gas pressure in the cavity. In alternative embodiments, gas distribution channels are formed in the WCD heat transfer surface to increase gas pressure uniformity between the wafer and the WCD thus improving temperature uniformity across the substrate.Type: GrantFiled: February 16, 1996Date of Patent: September 22, 1998Assignee: Novellus Systems, Inc.Inventors: Thomas Mountsier, James Wing