Patents by Inventor Thomas N. Adam

Thomas N. Adam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908045
    Abstract: A powered balancing mobility device that can provide the user the ability to safely navigate expected environments of daily living including the ability to maneuver in confined spaces and to climb curbs, stairs, and other obstacles, and to travel safely and comfortably in vehicles. The mobility device can provide elevated, balanced travel.
    Type: Grant
    Filed: May 20, 2017
    Date of Patent: February 2, 2021
    Assignee: DEKA Products Limited Partnership
    Inventors: Stewart M. Coulter, Brian G. Gray, Dirk A. van der Merwe, Daniel F. Pawlowski, Susan D. Dastous, Dean Kamen, Matthew A. Norris, Alexander D. Streeter, Matthew B. Kinberger, Catharine N. Flynn, David B. Doherty, David J. Couture, Elizabeth Rousseau, Thomas A. Doyon, Ryan J. Adams, Prashant Bhat
  • Publication number: 20200208025
    Abstract: An adhesive composition may include at least about 2 wt. % and not greater than 49 wt. % of a (meth)acrylic based polymeric component A for a total weight of the adhesive composition, at least about 51 wt. % of a (meth)acrylic based polymeric component B for a total weight of the adhesive composition, and at least about 0.1 wt. % and not greater than about 30 wt. % of a tackifier component for a total weight of the adhesive composition. The (meth)acrylic based polymeric component A may have a glass transition temperature (Tg) of at least about 40° C. The (meth)acrylic based polymeric component B may have a glass transition temperature (Tg) of not greater than about 20° C. Further, the (meth)acrylic based polymeric component B may be acid-free.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 2, 2020
    Inventors: Yubo CUI, Thomas L. Adams, David A. Elliott, James N. Gordon
  • Publication number: 20190087749
    Abstract: A computer-implemented method, and a computer system are provided for implementing dynamic and automatic altering a user profile based on machine learning and cognitive analysis to improve user performance. The user profile is dynamically altered based upon live data from multiple external data sources using machine learning and cognitive application programming interfaces (APIs) without explicit input from the user. The altered user profile is automatically stored for the user. The stored user profile is deployed for multiple selected user applications enabling enhanced performance for the user.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 21, 2019
    Inventors: Thomas N. Adams, Sarah W. Huber, Meghna Paruthi, Maria R. Ward
  • Publication number: 20190087748
    Abstract: A computer-implemented method, and a computer system are provided for implementing dynamic and automatic altering a user profile based on machine learning and cognitive analysis to improve user performance. The user profile is dynamically altered based upon live data from multiple external data sources using machine learning and cognitive application programming interfaces (APIs) without explicit input from the user. The altered user profile is automatically stored for the user. The stored user profile is deployed for multiple selected user applications enabling enhanced performance for the user.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: Thomas N. Adams, Sarah W. Huber, Meghna Paruthi, Maria R. Ward
  • Publication number: 20170229450
    Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: Thomas N. ADAM, Kangguo CHENG, Bruce B. DORIS, Ali KHAKIFROOZ, Alexander REZNICEK
  • Patent number: 9728649
    Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9673196
    Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 6, 2017
    Assignee: GlobalFoundries, Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9673296
    Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Jinghong Li, Alexander Reznicek
  • Patent number: 9530843
    Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Davood Shahrjerdi
  • Patent number: 9508851
    Abstract: A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9496282
    Abstract: FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9472576
    Abstract: A FinFET device includes a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins. At least one sidewall of each of the plurality of fins remain uncovered by the nitride material. The nitride material may also not contact the bottom of the plurality of fins.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9437679
    Abstract: A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9406665
    Abstract: Integrated passive devices for silicon on insulator (SOI) FinFET technologies and methods of manufacture are disclosed. The method includes forming a passive device on a substrate on insulator material. The method further includes removing a portion of the insulator material to expose an underside surface of the substrate on insulator material. The method further includes forming material on the underside surface of the substrate on insulator material, thereby locally thickening the substrate on insulator material under the passive device.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Kangguo Cheng, Balasubramanian Pranatharthi Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9406545
    Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9401373
    Abstract: A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9385231
    Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.
    Type: Grant
    Filed: November 2, 2014
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9373637
    Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20160163879
    Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.
    Type: Application
    Filed: January 29, 2016
    Publication date: June 9, 2016
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9362309
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek