Abstract: Priority inheritance is implemented across a distributed system, preferably by use of a mutual exclusion object, referred to as a pseudo-mutex, which provides operations for communicating priority of a task which is held to a different connected processor or node of a network and generating a dummy local command of priority at least equal to that of the held task at the remote processor or node in collaboration with a real-time operating system and middleware. The remote real time operating system then carries out priority inheritance in the normal manner to raise the priority of a blocked task, thus reversing any preemption of that task at the remote processor or node. The increase in priority avoids preemption of lower priority processes and thus increases the execution speed of the executing thread to release the existing lock at an earlier time; allowing a lock to be obtained by the higher priority thread.

Abstract: A data processing system including a write-once data-recording medium facilitates the creation and archiving of authenticated data records. In various aspects, a data-file depositor authenticates contents of a data file destined for recordation on the data-recording medium by associating with the data file a unique, depositor-specific signal indicative of the data-file depositor's intent to authenticate the data file contents. Additionally, various implementations facilitate the association with the data file of a witness-specific signal which, when so associated, constitutes evidence of a witness candidate's intent to verify at least the existence of the data file as of a time certain. In various implementations, a time of occurrence of at least one predetermined event related to at least one of the creation, saving and witnessing of the data file is associated with the data file. In accordance with some implementations, data files are placed in the custody of a data custodian.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation.

Abstract: A method for tracking objects is disclosed. First a region containing the objects is scanned to generate a multiplicity of sequential images or data sets of the region. A plurality of points in each of the images or data sets corresponds to a respective plurality of the objects. Next, respective figures of merit are determined for assigning the points to the tracks. Next, a k-dimensional cost function is defined which sums the figures of merit for combinations of assignments from the images or data sets. Next, the complexity of the cost function is reduced by Lagrangian Relaxation by permitting a point to be assigned to more than one track and adding a penalty factor to the cost function when a point is assigned to more than one track. The reducing step is iteratively repeated and the resultant penalized cost function is solved.