Abstract: One embodiment provides A DC-DC converter system that includes a high side switch and a low side switch coupled to a power supply, each switch is configured to transition from an on state to an off state and from an off state to an on state to deliver current to an inductor and a load. This embodiment also includes low side driver circuitry configured to control the conduction state of the low side switch and configured to drive the low side switch with a first gate driving signal during a first mode of operation and with a second gate driving signal during a second mode of operation. The first gate driving voltage is stronger than the second gate driving signal and the second gate driving signal is configured to cause a slower switch transition of the low side switch compared to the first gate drive control signal.

Abstract: One embodiment provides A DC-DC converter system that includes a high side switch and a low side switch coupled to a power supply, each switch is configured to transition from an on state to an off state and from an off state to an on state to deliver current to an inductor and a load. This embodiment also includes low side driver circuitry configured to control the conduction state of the low side switch and configured to drive the low side switch with a first gate driving signal during a first mode of operation and with a second gate driving signal during a second mode of operation. The first gate driving voltage is stronger than the second gate driving signal and the second gate driving signal is configured to cause a slower switch transition of the low side switch compared to the first gate drive control signal.

Abstract: A system and method are disclosed to limit a maximum duty cycle and/or provide a volt-second clamp for a pulse-width modulated (PWM) signal. Depending on the circuit topology, this approach can limit the absolute duty cycle or operate as a volt-second clamp in which the duty cycle is limited as a function of a variable input control voltage, such as a line voltage. The duty cycle can be selectively programmed by setting one or more external reference components, such as one or more respective resistors. Additionally, through component matching, desired clamping can be achieved with a high level of accuracy.

Abstract: A high speed memory with row redundancy has a plurality of memory cells arranged in rows, with additional redundant rows. When a defect is detected in a row, a redundant row is used in place of the defective row. Each row select signal is decoded by a predecoder, receiving a row address, and a decoder, comprising a NOR gate and an output driver. The NOR gate performs a logical NOR on a set of predecoded signals. The output driver receives the output of the NOR gate and has a bipolar portion and a CMOS portion to provide a row select signal, with a fast rise time and with a CMOS voltage level, to each of a plurality of memory blocks. A defective row is deselected by blowing two fuses which are internal to the NOR gate. The fuses are placed adjacent to each other so that the two fuses may be blown in a single operation.