Abstract: Approaches are provided for calculating a corresponding date of progress towards completion of a task regardless of a quantity being used to track the progress. An approach includes enumerating a list of time intervals for each sub-task of at least one summary task. The approach further includes distributing a progress value over a duration of each sub-task. The approach further includes creating, by at least one computing device, a coalesced set of time intervals for the at least one summary task based on the list of time intervals enumerated for each sub-task. The approach further includes traversing the coalesced set of time intervals and accumulating portions of the progress value until a required progress is obtained. The approach further includes determining a date of progress for the at least one summary task based on the accumulated portions of the progress value.

Abstract: A topology based approach to shielding wire generation for an integrated circuit design. The present invention generates various templates by sizing one or more signal wire geometries. The various templates are then geometrically added to and/or subtracted from to generate shielding wire patterns. In some embodiments, the templates may be merged to prevent duplicate shielding wire generation between adjacent signal wires that violates design rules. In some embodiments, the topology based approach permits shielding wire generation based upon complex signal wire geometries, such as branched signal wire geometries. The present invention can be implemented in CAD software and in CAD software together with a small amount of custom software to generate design rule clean (DRC) shielding wire generation that utilizes both power and ground nets.

Abstract: A topology based approach to shielding wire generation for an integrated circuit design. The present invention generates various templates by sizing one or more signal wire geometries. The various templates are then geometrically added to and/or subtracted from to generate shielding wire patterns. In some embodiments, the templates may be merged to prevent duplicate shielding wire generation between adjacent signal wires that violates design rules. In some embodiments, the topology based approach permits shielding wire generation based upon complex signal wire geometries, such as branched signal wire geometries. The present invention can be implemented in CAD software and in CAD software together with a small amount of custom software to generate design rule clean (DRC) shielding wire generation that utilizes both power and ground nets.