Abstract: Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.

Abstract: A technique is disclosed for operand propagation and accumulation within a processing array of an integrated circuit using overlapping patch regions. The system includes an interconnecting processing patch defined over a rectilinear subset of processing elements, with an origin processing element broadcasting operand data to the remaining elements in a directionally constrained, time-staggered wavefront pattern. A logical processing patch is separately defined over a second rectilinear subset of processing elements. The interconnecting processing patch and the logical processing patch partially overlap to form an interconnecting patch mesh comprising a common set of processing elements. Operand data is propagated from the origin of the interconnecting patch to the common processing elements within the patch mesh, enabling operand handoff or accumulation across patch boundaries.

Abstract: A technique is disclosed for operand propagation and accumulation within a processing array of an integrated circuit using overlapping patch regions. The system includes an interconnecting processing patch defined over a rectilinear subset of processing elements, with an origin processing element broadcasting operand data to the remaining elements in a directionally constrained, time-staggered wavefront pattern. A logical processing patch is separately defined over a second rectilinear subset of processing elements. The interconnecting processing patch and the logical processing patch partially overlap to form an interconnecting patch mesh comprising a common set of processing elements. Operand data is propagated from the origin of the interconnecting patch to the common processing elements within the patch mesh, enabling operand handoff or accumulation across patch boundaries.

Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop

Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop

Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop

Abstract: Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.

Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.

Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.

Abstract: A system and method for providing in-service firmware upgradability in a network element having a programmable device configured to support a plurality of application service engines or instances. A static core infrastructure portion of the programmable device is architected in a multi-layered functionality for effectuating a packet redirection scheme for packets intended for service processing by a particular application service engine that is being upgraded, whereby the remaining application service engines continue to provide service functionality without interruption.

Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.

Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.

Abstract: A multi-staged gas turbine engine fuel supply fuel injector includes at least first and second staged fuel injection circuits having first and second fuel injection points. At least first and second fuel nozzle valves operable to open at different first and second crack open pressures are controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector includes a valve housing containing the fuel nozzle valves.

Abstract: A multi-staged gas turbine engine fuel supply system includes a plurality of fuel injectors and at least first and second staged fuel injection circuits in each of the fuel injectors. Each of the first and second staged fuel injection circuits includes first and second fuel injection points and at least first and second fuel nozzle valves operable to open at different first and second crack open pressures and controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector may have a valve housing with one of the first fuel nozzle valves and one of the second fuel nozzle valves contained therein.

Abstract: A method and apparatus for locating containers in a container storage area and identifying the containers by means of their ID tags and identifying the address of the repository location of the containers in the container storage area and wirelessly transmitting the ID and address of the containers to the container terminal management system for verification that the container is deposited at the proper repository.

Abstract: Sulfate reducing bacteria are detected by preparing a lysate so as to release an enzyme essential to derive energy by reduction of sulfate such as adenosine 5'-phosphosulfate reductase (APS reductase), containing the lysate with an antibody for the enzyme, and detecting the presence of the reaction product of the enzyme and the antibody. In one aspect, sulfate reducing bacteria are controlled responsive to such assay. In another aspect, a "test kit" is provided for carrying out the assay.