Patents by Inventor Thomas Ng
Thomas Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12128342Abstract: A medical breathing gas filter housing includes a first housing body including a first port, and a second housing body including a second port. The gas filter housing is configurable between a closed state and an open state. In the closed state, the first housing body is snap fit to the second housing body such that first and second interior sides of the first and second housing bodies, respectively, define a cavity, the cavity sized to receive a replaceable gas filter media. In the open state, the first housing body is separated from the second housing body to provide access to the cavity.Type: GrantFiled: August 10, 2021Date of Patent: October 29, 2024Assignee: Vayu Global Health Innovations, Public Benefit CorporationInventors: Michelle Dundek, Akash Premkumar, Ellie Ng, Thomas Burke
-
Patent number: 12130876Abstract: Systems and methods for dynamic user profile projection are provided. One or more aspects of the systems and methods includes computing, by a prediction component, a predicted number of lookups for a future time period based on a lookup history of a user profile using a lookup prediction model; comparing, by the prediction component, the predicted number of lookups to a lookup threshold; and transmitting, by a projection component, the user profile to an edge server based on the comparison.Type: GrantFiled: October 24, 2022Date of Patent: October 29, 2024Assignee: ADOBE INC.Inventors: Nathan Ng, Tung Mai, Thomas Greger, Kelly Quinn Nicholes, Antonio Cuevas, Saayan Mitra, Somdeb Sarkhel, Anup Bandigadi Rao, Ryan A. Rossi, Viswanathan Swaminathan, Shivakumar Vaithyanathan
-
Patent number: 12113856Abstract: A computerized method is disclosed that includes operations of detecting user input to a first webpage rendered within a web browser, the user input corresponds to closure of the first webpage, providing an indication of the user input corresponding to the closure of the first webpage to a web browser extension operating in accordance with the web browser, the indication includes an identifier, performing, by the web browser extension operating in accordance with the web browser, a search for the identifier within a URL of each webpage currently opened by the web browser in order to determine that a second webpage is associated with the first webpage based on inclusion of the identifier in a URL of the second webpage, and initiating, by the web browser extension, closure of the second webpage associated with the first webpage following the user input corresponding to closure of the first webpage.Type: GrantFiled: May 13, 2022Date of Patent: October 8, 2024Assignee: Splunk Inc.Inventors: Jonathan Ng, Thomas Haggie
-
Publication number: 20230376665Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loopType: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
-
Patent number: 11755806Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loopType: GrantFiled: September 26, 2022Date of Patent: September 12, 2023Assignee: quadric.io, Inc.Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
-
Publication number: 20230055528Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loopType: ApplicationFiled: September 26, 2022Publication date: February 23, 2023Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
-
Publication number: 20220043475Abstract: Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventors: Srinivasan S. IYENGAR, Paul KAPPLER, Alon MEIR, Joseph MIRSKY, Thomas NG
-
Patent number: 10543370Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.Type: GrantFiled: December 22, 2017Date of Patent: January 28, 2020Assignee: PACESETTER, INC.Inventors: David Doudna, Dean Andersen, Thomas Ng
-
Publication number: 20190196734Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: David Doudna, Dean Andersen, Thomas Ng
-
Publication number: 20170093616Abstract: A system and method for providing in-service firmware upgradability in a network element having a programmable device configured to support a plurality of application service engines or instances. A static core infrastructure portion of the programmable device is architected in a multi-layered functionality for effectuating a packet redirection scheme for packets intended for service processing by a particular application service engine that is being upgraded, whereby the remaining application service engines continue to provide service functionality without interruption.Type: ApplicationFiled: September 28, 2015Publication date: March 30, 2017Inventors: Desmond Yan, Tak Kuen Tang, Thomas Ng
-
Patent number: 9058166Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.Type: GrantFiled: March 5, 2012Date of Patent: June 16, 2015Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)Inventors: Desmond Yan, Thomas Ng
-
Publication number: 20130232504Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Inventors: Desmond Yan, Thomas Ng
-
Publication number: 20050217269Abstract: A multi-staged gas turbine engine fuel supply fuel injector includes at least first and second staged fuel injection circuits having first and second fuel injection points. At least first and second fuel nozzle valves operable to open at different first and second crack open pressures are controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector includes a valve housing containing the fuel nozzle valves.Type: ApplicationFiled: March 31, 2004Publication date: October 6, 2005Inventors: William Myers, Thomas Ng, Alfred Mancini, James Cooper
-
Publication number: 20050198964Abstract: A multi-staged gas turbine engine fuel supply system includes a plurality of fuel injectors and at least first and second staged fuel injection circuits in each of the fuel injectors. Each of the first and second staged fuel injection circuits includes first and second fuel injection points and at least first and second fuel nozzle valves operable to open at different first and second crack open pressures and controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector may have a valve housing with one of the first fuel nozzle valves and one of the second fuel nozzle valves contained therein.Type: ApplicationFiled: March 15, 2004Publication date: September 15, 2005Inventors: William Myers, Thomas Ng, Alfred Mancini, James Cooper
-
Patent number: 6356802Abstract: A method and apparatus for locating containers in a container storage area and identifying the containers by means of their ID tags and identifying the address of the repository location of the containers in the container storage area and wirelessly transmitting the ID and address of the containers to the container terminal management system for verification that the container is deposited at the proper repository.Type: GrantFiled: August 4, 2000Date of Patent: March 12, 2002Assignee: Paceco Corp.Inventors: Toru Takehara, Thomas Ng
-
Patent number: 4999286Abstract: Sulfate reducing bacteria are detected by preparing a lysate so as to release an enzyme essential to derive energy by reduction of sulfate such as adenosine 5'-phosphosulfate reductase (APS reductase), containing the lysate with an antibody for the enzyme, and detecting the presence of the reaction product of the enzyme and the antibody. In one aspect, sulfate reducing bacteria are controlled responsive to such assay. In another aspect, a "test kit" is provided for carrying out the assay.Type: GrantFiled: December 23, 1986Date of Patent: March 12, 1991Assignee: E. I. du Pont de Nemours and CompanyInventors: Len J. Gawel, Thomas Ng, James M. Odom, Richard C. Ebersole
-
Patent number: D317025Type: GrantFiled: December 5, 1988Date of Patent: May 21, 1991Assignee: Blue Box Toy Factory LimitedInventor: Thomas Ng Chuk-Sun