Patents by Inventor Thomas Ng

Thomas Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250021786
    Abstract: The present disclosure refers to a printed circuit for integration in a smart card, wherein the printed circuit comprises a printed circuit substrate of dielectric material, an antenna having a resonance frequency, one or more contact pads forming an external contact pattern, and at least one surface mount (SMD) capacitor connected to the antenna so as to adjust its resonance frequency, in order to match a predefined resonance frequency, for instance a resonance frequency comprised within the range defined in ISO 14443 standards. The present disclosure also refers to a module comprising the above-indicated printed circuit and an IC chip and to a corresponding smart card.
    Type: Application
    Filed: November 30, 2021
    Publication date: January 16, 2025
    Inventors: Yean Wei YEAP, Cindy NG, Thomas DECKER
  • Publication number: 20230376665
    Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
  • Patent number: 11755806
    Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: September 12, 2023
    Assignee: quadric.io, Inc.
    Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
  • Publication number: 20230055528
    Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop
    Type: Application
    Filed: September 26, 2022
    Publication date: February 23, 2023
    Inventors: Thomas Ng, Nigel Drego, Daniel Firu, Veerbhan Kheterpal, Aman Sikka
  • Publication number: 20220043475
    Abstract: Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.
    Type: Application
    Filed: October 22, 2021
    Publication date: February 10, 2022
    Inventors: Srinivasan S. IYENGAR, Paul KAPPLER, Alon MEIR, Joseph MIRSKY, Thomas NG
  • Patent number: 10543370
    Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 28, 2020
    Assignee: PACESETTER, INC.
    Inventors: David Doudna, Dean Andersen, Thomas Ng
  • Publication number: 20190196734
    Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: David Doudna, Dean Andersen, Thomas Ng
  • Publication number: 20170093616
    Abstract: A system and method for providing in-service firmware upgradability in a network element having a programmable device configured to support a plurality of application service engines or instances. A static core infrastructure portion of the programmable device is architected in a multi-layered functionality for effectuating a packet redirection scheme for packets intended for service processing by a particular application service engine that is being upgraded, whereby the remaining application service engines continue to provide service functionality without interruption.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: Desmond Yan, Tak Kuen Tang, Thomas Ng
  • Patent number: 9058166
    Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: June 16, 2015
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Desmond Yan, Thomas Ng
  • Publication number: 20130232504
    Abstract: In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 5, 2013
    Inventors: Desmond Yan, Thomas Ng
  • Publication number: 20050217269
    Abstract: A multi-staged gas turbine engine fuel supply fuel injector includes at least first and second staged fuel injection circuits having first and second fuel injection points. At least first and second fuel nozzle valves operable to open at different first and second crack open pressures are controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector includes a valve housing containing the fuel nozzle valves.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: William Myers, Thomas Ng, Alfred Mancini, James Cooper
  • Publication number: 20050198964
    Abstract: A multi-staged gas turbine engine fuel supply system includes a plurality of fuel injectors and at least first and second staged fuel injection circuits in each of the fuel injectors. Each of the first and second staged fuel injection circuits includes first and second fuel injection points and at least first and second fuel nozzle valves operable to open at different first and second crack open pressures and controllably connected to the first and second staged fuel injection circuits, respectively. A single fuel supply manifold is connected to all of the fuel nozzle valves. A single fuel signal manifold is controllably connected to all of the first and second fuel nozzle valves. The fuel injector may have a valve housing with one of the first fuel nozzle valves and one of the second fuel nozzle valves contained therein.
    Type: Application
    Filed: March 15, 2004
    Publication date: September 15, 2005
    Inventors: William Myers, Thomas Ng, Alfred Mancini, James Cooper
  • Patent number: 6356802
    Abstract: A method and apparatus for locating containers in a container storage area and identifying the containers by means of their ID tags and identifying the address of the repository location of the containers in the container storage area and wirelessly transmitting the ID and address of the containers to the container terminal management system for verification that the container is deposited at the proper repository.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: March 12, 2002
    Assignee: Paceco Corp.
    Inventors: Toru Takehara, Thomas Ng
  • Patent number: 4999286
    Abstract: Sulfate reducing bacteria are detected by preparing a lysate so as to release an enzyme essential to derive energy by reduction of sulfate such as adenosine 5'-phosphosulfate reductase (APS reductase), containing the lysate with an antibody for the enzyme, and detecting the presence of the reaction product of the enzyme and the antibody. In one aspect, sulfate reducing bacteria are controlled responsive to such assay. In another aspect, a "test kit" is provided for carrying out the assay.
    Type: Grant
    Filed: December 23, 1986
    Date of Patent: March 12, 1991
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Len J. Gawel, Thomas Ng, James M. Odom, Richard C. Ebersole
  • Patent number: D317025
    Type: Grant
    Filed: December 5, 1988
    Date of Patent: May 21, 1991
    Assignee: Blue Box Toy Factory Limited
    Inventor: Thomas Ng Chuk-Sun