Abstract: A method for inspecting containers with closures with a cap portion and a circumferential edge extending around the mouth of the containers. The containers are transported along a transport path by a transport device. During transport, the mouth regions of the containers with closures are illuminated by an illumination device, and at least one image recording device records at least one image of the mouth regions of the containers with closures, and records at least one spatially resolved image of a portion of the circumferential edge and one structure on the circumferential edge is detected, and, at least one value of this structure, a value characteristic of a relative position of the closure relative to the container and/or relative to the rotationally symmetrical element and/or of the closure is determined.

Abstract: A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the se

Abstract: The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.

Abstract: A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path is determined by a switchable resistivity value of a switchable resistor that is included by the circuit. The invention further provides method for configuring a circuit and to a logic circuit.

Abstract: The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be connected to the master latch for the purpose of buffer storing the data bit; at least one second slave latch which can be connected to the master latch for the purpose of buffer storing the data bit, and having an evaluation logic unit which outputs the configuration bit on the basis of the data bits which are buffer stored in the master latch and in the slave latches. In addition, the invention provides a shift register for safely providing configuration bits which has a plurality of inventive shift register cells which are connected in series to form a shift register chain.

Abstract: The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.

Abstract: A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the se

Abstract: The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for non-volatile saving of the stored information and a means for saving the information in the resistance element. A means for retrieving the saved information is additionally present.

Abstract: Shift register for safely providing a configuration bit The invention relates to a shift register cell (1-i, 100-i) for safely providing a configuration bit (6-i) having a master latch (8-i) which can be connected to a serial data input (2-i) on the shift register cell (1-i, 100-i) for the purpose of buffer-storing a data bit (3-i); a first slave latch (10-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit; at least one second slave latch (12-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit, and having an evaluation logic unit (13-i) which outputs the configuration bit (6-i) on the basis of the data bits which are buffer-stored in the master latch (8-i) and in the slave latches (10-i, 12-i). In addition, the invention provides a shift register (17) for safely providing configuration bits (6-1, . . . 6-N) which has a plurality of inventive shift register cells (1-1, . . . 1-N, 100-1, . . .

Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.