Abstract: This document discusses, among other things, an information technology (IT) enterprise manager system. In one example, the system includes data groups organized into IT Services, IT Resources, and IT Consumers data groups. The IT Resources data group may include one or more of an IT Applications data group, an IT Assets data group, an IT Staff Data group, and an IT Vendors data group. The IT Consumers data group may include one or both of a Business Processes data group and an IT Clients data group. Information in one data group may use a link to other information in another data group. In one example, the system provides tools and methods for managing a portfolio IT projects through various phases of their lifecycles, such as during project definition, establishing a business case for the project, project design and implementation, and/or project wrap-up.

Abstract: This document discusses, among other things, an information technology (IT) enterprise manager system. In one example, the system includes data groups organized into IT Services, IT Resources, and IT Consumers data groups. The IT Resources data group may include one or more of an IT Applications data group, an IT Assets data group, an IT Staff Data group, and an IT Vendors data group. The IT Consumers data group may include one or both of a Business Processes data group and an IT Clients data group. Information in one data group may use a link to other information in another data group. In one example, the system provides tools and methods for managing a portfolio IT projects through various phases of their lifecycles, such as during project definition, establishing a business case for the project, project design and implementation, and/or project wrap-up.

Abstract: A sequential circuit test generation system and method to generate test patterns for sequential without assuming the use of scan techniques or a reset state utilizes the iterative logic array (ILA) model of the sequential circuit and a targeted-D propagation scheme employing both forward time processing (FTP) and reverse time processing (RTP) techniques for assigning a sequence of primary input (PI) values and for producing a an initial pseudo primary input (PPI) vector representing the initial state of the digital circuit at a particular time frame. Improved state justification techniques generate the remaining sequence of PI vectors necessary to put the circuit into the initial state from either known or don't care first states, by means of a heuristic method for reducing required initial state assignments. The method can also be applied to reduce the required number of PI vector assignments is also presented.

Abstract: A riding simulator for a cycle (1) with a supporting frame (2) with parallel, spaced riding simulation rollers (3, 4), on which front and rear wheels (5, 6) of a cycle (1) can run, is mounted in a supporting frame (2) with a crosswise rail (7) placed parallel to rollers (3, 4), with a runner (8) that is freely movable back and forth on or in the crosswise rail (7) but is positionally fixed crosswise relative to the rail (7), and a runner (8) that can be fastened by a link (9) to the frame (10) of the cycle (1) at a specific distance from the crosswise rail (7) so as to be able to swing around a horizontal pivot pin (11), and a rotating joint (12) between the runner (8) and the link (9) which allows only a rotation of link (9) relative to runner (8) around the longitudinal axis of a unit formed of the runner (8) and link (9).