Abstract: Complex mixed metal containing thin films can be deposited by CVD from liquid mixtures of metal complexes without solvent by direct liquid injection and by other precursor dispersing method such as aerosol delivery with subsequent annealing to improve electrical properties of the deposited films. This process has potential for commercial success in microelectronics device fabrication of dielectrics, ferroelectrics, barrier metals/electrodes, superconductors, catalysts, and protective coatings. Application of this process, particularly the CVD of ZrSnTiOx (zirconium tin titanate, or ZTT) and HfSnTiOx (hafnium tin titanate, or HTT) thin films has been studied successfully.

Abstract: An agricultural sprayer for spraying a mixture of a carrier liquid and at least one active ingredient, and including a carrier liquid container, at least one active ingredient container for containing the active ingredient in concentrated form, a mixing chamber for mixing the carrier liquid with the active ingredient, at least one active ingredient feed line between the at least one active ingredient container and the mixing chamber and a carrier liquid feed line between the carrier liquid container and the mixing chamber, a boom structure having at least one nozzle connected with said mixing chamber for spraying the mixture of the active ingredient and the carrier liquid, and means for generating and discharging a flow of gas under pressure. The sprayer has connecting means that allow gas low communication between said means for generating and discharging a flow of gas under pressure and said at least one container for receiving an active ingredient.

Abstract: An improved process for the preparation of cis-1,3-diols is described where a beta hydroxy ketone is treated with a trialkylborane or dialkylalkoxyborane or a mixture of a trialkylborane and a dialkylalkoxyborane followed by recovery and reuse of the alkylborane species to convert additional beta hydroxy ketone to the cis-1,3-diol.

Abstract: A method of removing a biological contaminant from a mixture containing a biomolecule and the biological contaminant, the method comprising: (a) placing the biomolecule and contaminant mixture in a first solvent stream, the first solvent stream being separated from a second solvent stream by an electrophoretic membrane; (b) selecting a buffer for the first solvent stream having a required pH; (c) applying an electric potential between the two solvent streams causing movement of the biomolecule through the membrane into the second solvent stream while the biological contaminant is substantially retained in the first sample stream, or if entering the membrane, being substantially prevented from entering the second solvent stream; (d) optionally, periodically stopping and reversing the electric potential to cause movement of any biological contaminants having entered the membrane to move back into the first solvent stream, wherein substantially not causing any biomolecules that have entered the second solvent st

Abstract: An improved process for the preparation of cis-1,3-diols is described where a beta hydroxy ketone is treated with a trialkylborane or dialkylalkoxyborane or a mixture of a trialkylborane and a dialkylalkoxyborane followed by recovery and reuse of the alkylborane species to convert additional beta hydroxy ketone to the cis-1,3-diol.

Abstract: A method of removing a biological contaminant from a mixture containing a biomolecule and the biological contaminant, the method comprising: (a) placing the biomolecule and contaminant mixture in a first solvent stream, the first solvent stream being separated from a second solvent stream by an electrophoretic membrane; (b) selecting a buffer for the first solvent stream having a required pH; (c) applying an electric potential between the two solvent streams causing movement of the biomolecule through the membrane into the second solvent stream while the biological contaminant is substantially retained in the first sample stream, or if entering the membrane, being substantially prevented from entering the second solvent stream; (d) optionally, periodically stopping and reversing the electric potential to cause movement of any biological contaminants having entered the membrane to move back into the first solvent stream, wherein substantially not causing any biomolecules that have entered the second solvent st

Abstract: This invention is directed to a group of novel homologous eight membered ring compounds having a metal, such as copper, reversibly bound in the ring and containing carbon, nitrogen, silicon and/or other metals.

Abstract: A method of removing a biological contaminant from a mixture containing a biomolecule and the biological contaminant, the method comprising: (a) placing the biomolecule and contaminant mixture in a first solvent stream, the first solvent stream being separated from a second solvent stream by an electrophoretic membrane; (b) selecting a buffer for the first solvent stream having a required pH; (c) applying an electric potential between the two solvent streams causing movement of the biomolecule through the membrane into the second solvent stream while the biological contaminant is substantially retained in the first sample stream, or if entering the membrane, being substantially prevented from entering the second solvent stream; (d) optionally, periodically stopping and reversing the electric potential to cause movement of any biological contaminants having entered the membrane to move back into the first solvent stream, wherein substantially not causing any biomolecules that have entered the second solvent st

Abstract: A method for producing a tantalum nitride layer on a substrate, comprising; directly injecting a liquid mixture of (R1R2N)3Ta(═NR3) and (R4R5N)3Ta[&eegr;2—R6N═C (R7)(R8)] into a dispersing zone followed by delivering the dispersed mixture into a reactor containing the substrate at elevated temperature and reacting the mixture with a source of nitrogen selected from the group consisting of ammonia, alkyl amines, N2H2, alkyl hydrazine, N2 and mixtures thereof, to produce the tantalum nitride layer on the substrate, where R1, R2, R3, R4, R5, R6, R7 and R8 are individually C1-6 alkyl, aryl or hydrogen.

Abstract: The present invention is a composition for deposition of a mixed metal or metal compound layer, comprising a solventless mixture of at least two metal-ligand complex precursors, wherein the mixture is liquid at ambient conditions and the ligands are the same and are selected from the group consisting of alkyls, alkoxides, halides, hydrides, amides, imides, azides cyclopentadienyls, carbonyls, and their fluorine, oxygen and nitrogen substituted analogs.

Abstract: In a process for the synthesis of a first metal-ligand complex, M.sup.+n (L.sup.-).sub.n, where n.gtoreq.1, from a metal compound precursor and a ligand precursor, where the metal of the metal compound precursor may during the synthesis change to a valence in excess of n; the improvement, to suppress formation of a second metal-ligand complex of the metal with a valence in excess of n, of adding the elemental form of the metal to the synthesis of the first metal-ligand complex.

Abstract: A process for recovering a 1,1,1,5,5,5-hexafluoro-2,4-pentanedione ligand from a metal-ligand complex byproduct such as Cu.sup.+2 (1,1,1,5,5,5-hexafluoro-2,4-pentanedionate.sup.-1).sub.2, comprising: providing a copper-ligand complex byproduct of Cu.sup.+2 (1,1,1,5,5,5-hexafluoro-2,4-pentanedionate.sup.-1).sub.2 in a process stream; cooling and condensing the copper-ligand complex byproduct of Cu.sup.+2 (1,1,1,5,5,5-hexafluoro-2,4-pentanedionate.sup.-1).sub.2 to separate it from the process stream; contacting the copper-ligand complex byproduct of Cu.sup.+2 (1,1,1,5,5,5-hexafluoro-2,4-pentanedionate.sup.-1).sub.2 with a protonation agent, such as: sulfuric acid, hydrochloric acid, hydroiodic acid, hydrobromic acid, trifluoroacetic acid, trifluoromethanesulfonic acid, acid ion exchange resin, hydrogen sulfide, water vapor and mixtures thereof; and recovering 1,1,1,5,5,5-hexafluoro-2,4-pentanedione.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a "cluster ring".

Abstract: A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.

Abstract: In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to "slide" through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.