Patents by Inventor Thomas OBrien
Thomas OBrien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240321872Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.Type: ApplicationFiled: March 23, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Leonard P. Guler, Shengsi Liu, Saurabh Acharya, Thomas Obrien, Krishna Ganesan, Ankit Kirit Lakhani, Prabhjot Kaur Luthra, Nidhi Khandelwal, Clifford J. Engel, Baofu Zhu, Meenakshisundaram Ramanathan
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Publication number: 20240321978Abstract: Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.Type: ApplicationFiled: March 23, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Leonard P. Guler, Shengsi Liu, Baofu Zhu, Charles H. Wallace, Clifford J. Engel, Gary Allen, Saurabh Acharya, Thomas Obrien
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Patent number: 10132738Abstract: Platelets or blood cells are detected in a fluid sample by adjusting a focal depth of a microscope through a range of values, the microscope having a mounted sample and an objective lens adapted with one or both of (a) a spherical aberration correction unmatched to a utilized cover plate for the sample, or (2) a numerical aperture unmatched to a utilized illumination source for the sample. Images are recorded at different specific focal depths and in multiple z planes of a fluid bearing the platelets, where the position of platelets may overlap on different of the multiple z planes that are recorded, the images recorded through the cover plate, thus causing the generation of a specific light-dark pattern indicative of platelets at particular positions and at multiple depths in the fluid media. The images are analyzed for the specific light-dark pattern.Type: GrantFiled: June 26, 2017Date of Patent: November 20, 2018Assignee: FOCE Technology International BVInventors: Thomas Obrien, Hendrik Dijkstra, Marcel F Schemmann
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Publication number: 20170292905Abstract: Platelets or blood cells are detected in a fluid sample by adjusting a focal depth of a microscope through a range of values, the microscope having a mounted sample and an objective lens adapted with one or both of (a) a spherical aberration correction unmatched to a utilized cover plate for the sample, or (2) a numerical aperture unmatched to a utilized illumination source for the sample. Images are recorded at different specific focal depths and in multiple z planes of a fluid bearing the platelets, where the position of platelets may overlap on different of the multiple z planes that are recorded, the images recorded through the cover plate, thus causing the generation of a specific light-dark pattern indicative of platelets at particular positions and at multiple depths in the fluid media. The images are analyzed for the specific light-dark pattern.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Thomas Obrien, Hendrik Dijkstra, Marcel F. Schemmann
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Patent number: 9690974Abstract: Platelets or blood cells are detected in a fluid sample by adjusting a focal depth of a microscope through a range of values, the microscope having a mounted sample and an objective lens adapted with one or both of (a) a spherical aberration correction unmatched to a utilized cover plate for the sample, or (2) a numerical aperture unmatched to a utilized illumination source for the sample. Images are recorded at different specific focal depths and in multiple z planes of a fluid bearing the platelets, where the position of platelets may overlap on different of the multiple z planes that are recorded, the images recorded through the cover plate, thus causing the generation of a specific light-dark pattern indicative of platelets at particular positions and at multiple depths in the fluid media. The images are analyzed for the specific light-dark pattern.Type: GrantFiled: March 24, 2014Date of Patent: June 27, 2017Assignee: 2M Engineering LimitedInventors: Thomas Obrien, Hendrik Dijkstra, Marcel F Schemmann
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Publication number: 20140205176Abstract: Platelets or blood cells are detected in a fluid sample by adjusting a focal depth of a microscope through a range of values, the microscope having a mounted sample and an objective lens adapted with one or both of (a) a spherical aberration correction unmatched to a utilized cover plate for the sample, or (2) a numerical aperture unmatched to a utilized illumination source for the sample. Images are recorded at different specific focal depths and in multiple z planes of a fluid bearing the platelets, where the position of platelets may overlap on different of the multiple z planes that are recorded, the images recorded through the cover plate, thus causing the generation of a specific light-dark pattern indicative of platelets at particular positions and at multiple depths in the fluid media. The images are analyzed for the specific light-dark pattern.Type: ApplicationFiled: March 24, 2014Publication date: July 24, 2014Applicant: FOCE Technology International BVInventors: Thomas Obrien, Hendrik Dijkstra, Marcel F Schemmann
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Patent number: 7139991Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.Type: GrantFiled: April 14, 2005Date of Patent: November 21, 2006Assignee: LSI Logic CorporationInventors: Yaron Kretchmer, Michael Porter, Thomas Obrien
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Publication number: 20050204235Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.Type: ApplicationFiled: April 14, 2005Publication date: September 15, 2005Inventors: Yaron Kretchmer, Michael Porter, Thomas Obrien
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Patent number: 6931606Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.Type: GrantFiled: October 15, 2001Date of Patent: August 16, 2005Assignee: LSI Logic CorporationInventors: Yaron Kretchmer, Michael Porter, Thomas OBrien