Abstract: A serial to parallel bus converter (11) enables a slave computer (13), having a parallel bus input (19) to be controlled by a master computer (15) via a serial bus connection (14). The converter (11) interprets commands from the master computer (15) to provide appropriate control commands for the slave computer (13). Instructions received from the master computer (15) are provided to the slave computer (13) when complete commands from the master computer (15) are received by the converter (11). The converter (11) uses an intermediate bus (29), which is connected to the RAMs (27), ports (41-44) and a control register (45) for communicating with the slave computer (13), a UART port (31) for communicating with the master computer (15), a microprocessor (25) and a programmable read only memory (PROM) (33) for the microprocessor (25).

Abstract: An interface (10) between a first (MC, 30) and second (SC) computer employs a multiplexer (46) and a coupler (48, 50). The first (MC, 30) and second (SC) computers have a first (LA/B, LEX0-15) and second (CX1-21, CA1-15) plurality of information lines, respectively. These computers also each have a group of control lines (36, 42). The multiplexer (46) is connected to the first and second plurality of information lines (LA/B, LEX0-15, CX1-21, CA1-15). The multiplexer (46) is operable to separately switch each of a predetermined group (LEX12-15) within the first plurality (LA/B, LEX0-15) between either member of a different corresponding pair within the second plurality (CX1-21, CA1-15). The multiplexer (46) is also connected to at least one (ESELCX) of the control lines (36) of the first computer (MC, 30). The multiplexer (46) can switch the predetermined group (LEX12-15) in response to a signal on the control lines (ESELCX) of the first computer (MC, 30).

Abstract: A link (10) exchanges data between a master (MC) and slave (SC) computer. Each computer has control lines (26A, 42) and incompatible information lines (26B, 26C, CA1-15, CX1-21). The master computer (MC) includes a master interface (28) connected to the information and control lines (26) of the master computer (MC). The master interface (28) has separate intercommunication lines (LA/B) and intermediate (34) lines. This master interface (28) is able to provide an intermediate signal on its intermediate lines (34) in response to signals provided by the master computer (MC) on its control lines (26A). The link (10) includes a computing subsystem (30) and a slave interface (38). The computing subsystem (30) is connected to the intercommunication (LA/B) and intermediate (34) lines of the master interface (28). The computing subsystem (30) has command lines (36) for providing thereon a command signal in response to the intermediate signal.

Abstract: In this method, a unit (24) is tested by a test instrument (22) with the aid of a master (MC), an intermediate (30) and a slave (SL) computer. The latter connects to the test instrument (22) for sensing its measurements. The method includes the step of dispatching one of a plurality of instruction signals to the intermediate computer (30) from the master computer (MC). Another step is issuing to the slave computer (SL), when it is not halted, a signal to halt from the intermediate computer (30) after receipt by the intermediate computer (30) of one of the instruction signals. Another step is transmitting from the intermediate (30) to the slave (SL) computer, after the latter has halted, that one of a plurality of command signals corresponding to the currently dispatched one of the instruction signals.