Abstract: A Quad Flat Pack (QFP) package which includes first and second dies arranged in a side-by-side orientation, and a power supply bus which protrudes between adjacent sides of the first and second dies and which supplies power to the adjacent sides via connections to the adjacent sides.

Abstract: A system to determine the length of time, known as the latency time, that is required to wait between transmitting and receiving data for a half-duplex electromagnetic transceiver having a transmitter and receiver wherein the receiver is electromagnetically coupled to the transmitter. The determination of the latency time is accomplished by the use of a control circuit that operates to turn the transmitter to an on state. The control circuit then monitors the receiver to determine when the receiver also goes to an on state due to the electromagnetic coupling. The control circuit subsequently turns off the transmitter and the length of time for the receiver to recover to an off state is measured. This length of time is the latency time and is used in subsequent transmission of data.

Abstract: A system is described that includes an integrated circuit chip having output paths connected to a network whose electrical of capacitance characteristics can vary. The system includes a circuit for adjusting output drive applied to a pad on the chip. The circuit includes a PVT monitor for providing an output that is related to process, voltage and temperature parameter variations on the chip. A processor determines network configuration information and enables the network's electrical or capacitance characteristics to be determined. The processor is responsive to an output from the PVT monitor and the network's determined electrical characteristics to provide control outputs indicative of a required output drive current level. A drive current circuit includes alterable circuitry and is responsive to the processor's control output to provide the required output drive levels to the pad.