Patents by Inventor Thomas Ort

Thomas Ort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250012248
    Abstract: A method of refurbishing a facility for converting hydraulic energy into electrical energy including the following steps: providing a first cover plate, a second cover plate, a first opening located at an inner head cover, a second opening located at a hub, a third opening located at a runner; connecting the first cover plate to the inner head cover; connecting the second cover plate to the hub, wherein the first cover plate and the second cover plate surround an axis, and a part of an outer surface of the inner head cover, a part of an outer surface of the hub, an inner surface of the first cover plate, and an inner surface of the second cover plate are confining an annular shaped space.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 9, 2025
    Applicant: Voith Patent GmbH
    Inventors: Thomas Ort, Veerandra Chakkaravarthy Andichamy, Rebecca Fuhrman, Kayli Rentzel
  • Publication number: 20240355697
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 12057364
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20240194552
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Lizabeth KESER, Bernd WAIDHAS, Thomas ORT, Thomas WAGNER
  • Patent number: 11955395
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Patent number: 11764187
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 19, 2023
    Assignee: Intel Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Publication number: 20230090265
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 11508637
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20220336306
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Lizabeth KESER, Bernd WAIDHAS, Thomas ORT, Thomas WAGNER
  • Patent number: 11404339
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Publication number: 20220051990
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 17, 2022
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 11211337
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10867934
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Publication number: 20200303274
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Publication number: 20200251396
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10720393
    Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20200227388
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Patent number: 10699980
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Patent number: 10665522
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20200158073
    Abstract: A propeller-type runner for a hydraulic turbine or pump has a hub and a plurality of blades. Up to and including two blades are fixed to the hub using bolts. The remaining blades are welded to the hub. Each bolted blade is adjoined by two welded blades.
    Type: Application
    Filed: April 17, 2018
    Publication date: May 21, 2020
    Inventors: STUART COULSON, SETH SMITH, WALTER RIEGLER, THOMAS ORT