Patents by Inventor Thomas Ostermann
Thomas Ostermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11695069Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.Type: GrantFiled: May 10, 2021Date of Patent: July 4, 2023Assignee: Infineon Technologies AGInventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
-
Publication number: 20230148014Abstract: A MEMS component is described herein, which according to one exemplary embodiment includes: a semiconductor body; an insulation layer arranged on the semiconductor body; a boundary structure arranged on the insulation layer, the semiconductor body including an opening below the boundary structure; first and second structured electrodes arranged on the insulation layer; and a piezoelectric layer comprising a thermoplastic, and at least partially bounded by the boundary structure and arranged on the insulation layer and on the first and second electrodes.Type: ApplicationFiled: October 25, 2022Publication date: May 11, 2023Inventors: Thomas Grille, Elmar Aschauer, Ulf Bartl, Christoph Kovatsch, Matic Krivec, Thomas Ostermann, Lukas Praster, Gerald Stocker
-
Publication number: 20230019665Abstract: A device for controlling trapped ions includes a substrate. An electrode structure is disposed on the substrate, the electrode structure including DC electrodes and RF electrodes of an ion trap configured to trap ions in a space above the substrate. A first device terminal is disposed on the substrate, the first device terminal being connected via a first electrode connection line to a specific DC electrode. Further, a second device terminal is disposed on the substrate, the second device terminal being connected via a second electrode connection line to the specific DC electrode.Type: ApplicationFiled: July 15, 2022Publication date: January 19, 2023Inventors: Clemens Roessler, Thomas Ostermann, Norbert Rieser, Johanna Elisabeth Roessler, Siegfried Schmid, Walter Slamnig
-
Publication number: 20210265497Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
-
Patent number: 11018250Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.Type: GrantFiled: May 6, 2019Date of Patent: May 25, 2021Assignee: Infineon Technologies AGInventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
-
Patent number: 10957686Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.Type: GrantFiled: January 16, 2020Date of Patent: March 23, 2021Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Publication number: 20210050434Abstract: An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Gerhard Prechtl, Andreas Peter Meiser, Thomas Ostermann
-
Publication number: 20200357917Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.Type: ApplicationFiled: May 6, 2019Publication date: November 12, 2020Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
-
Patent number: 10672661Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.Type: GrantFiled: October 31, 2018Date of Patent: June 2, 2020Assignee: Infineon Technologies AGInventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
-
Publication number: 20200152621Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Publication number: 20200135564Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
-
Patent number: 10586792Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.Type: GrantFiled: December 31, 2018Date of Patent: March 10, 2020Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Patent number: 10461203Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.Type: GrantFiled: March 20, 2018Date of Patent: October 29, 2019Assignee: Infineon Technologie AGInventors: Stefan Clara, Thomas Grille, Ursula Hedenig, Peter Irsigler, Bernhard Jakoby, Ventsislav M. Lavchiev, Thomas Ostermann, Thomas Popp
-
Patent number: 10393697Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.Type: GrantFiled: November 2, 2015Date of Patent: August 27, 2019Assignee: Infineon Technologies AGInventors: Sabine Gruber, Thomas Aichinger, Stefan Krivec, Thomas Ostermann
-
Publication number: 20190157259Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.Type: ApplicationFiled: December 31, 2018Publication date: May 23, 2019Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Patent number: 10217830Abstract: A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region.Type: GrantFiled: December 8, 2016Date of Patent: February 26, 2019Assignee: Infineon Technologies AGInventors: Markus Zundel, Thomas Ostermann, Michael Sorger
-
Patent number: 10199490Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.Type: GrantFiled: March 8, 2018Date of Patent: February 5, 2019Assignee: Infineon Technologies AGInventors: Adrian Finney, Radu Eugen Cazimirovici, Dietmar Kotz, Thomas Ostermann
-
Patent number: 10186508Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.Type: GrantFiled: October 24, 2017Date of Patent: January 22, 2019Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Publication number: 20180212085Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Inventors: Stefan CLARA, Thomas Grille, Ursula Hedenig, Peter Irsigler, Bernhard Jakoby, Ventsislav M. Lavchiev, Thomas Ostermann, Thomas Popp
-
Publication number: 20180197982Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Adrian Finney, Radu Eugen Cazimirovici, Dietmar Kotz, Thomas Ostermann