Patents by Inventor Thomas Oszinda
Thomas Oszinda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11581369Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.Type: GrantFiled: December 10, 2020Date of Patent: February 14, 2023Assignee: Infineon Technologies Austria AGInventors: Sylvain Leomant, Gerhard Noebauer, Thomas Oszinda, Christian Gruber, Sergey Ananiev
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Patent number: 11322655Abstract: Optoelectronic components may include a semiconductor layer sequence on an auxiliary carrier where the sequence includes at least one n-doped layer, at least one p-doped layer, and an active layer therebetween. A first insulation layer is arranged over a surface of the n-doped layer. A first and second metallization are arranged for contacting the p-doped and n-doped layers, and the metallizations are connected to each other. The first and second metallizations are spatially separated from one another. A second insulation layer electrically insulates the first and second metallizations.Type: GrantFiled: July 5, 2018Date of Patent: May 3, 2022Assignee: OSRAM OLED GmbHInventors: Thomas Oszinda, Attila Molnar, Fabian Kopp
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Publication number: 20210183948Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.Type: ApplicationFiled: December 10, 2020Publication date: June 17, 2021Inventors: Sylvain Leomant, Gerhard Noebauer, Thomas Oszinda, Christian Gruber, Sergey Ananiev
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Patent number: 11011504Abstract: An optoelectronic semiconductor chip includes a semiconductor body including a first semiconductor region and a second semiconductor region, a recess extending through the first semiconductor region, the recess having a bottom surface, where the second semiconductor region is exposed, and a blocking element arranged on the bottom surface, wherein the at least one recess has a first width and a second width parallel to the main extension plane of the semiconductor body, and the first width is smaller than the second width.Type: GrantFiled: January 22, 2019Date of Patent: May 18, 2021Assignee: OSRAM OLED GmbHInventors: Thomas Oszinda, Ban Loong Chris Ng
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Publication number: 20210091269Abstract: Optoelectronic components may include a semiconductor layer sequence on an auxiliary carrier where the sequence includes at least one n-doped layer, at least one p-doped layer, and an active layer therebetween. A first insulation layer is arranged over a surface of the n-doped layer. A first and second metallization are arranged for contacting the p-doped and n-doped layers, and the metallizations are connected to each other. The first and second metallizations are spatially separated from one another. A second insulation layer electrically insulates the first and second metallizations.Type: ApplicationFiled: July 5, 2018Publication date: March 25, 2021Inventors: Thomas Oszinda, Attila Molnar, Fabian Kopp
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Patent number: 10867923Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.Type: GrantFiled: September 19, 2018Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Tae Soo Kim, Jong Min Baek, Woo Kyung You, Thomas Oszinda, Byung Hee Kim, Nae In Lee
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Publication number: 20190229102Abstract: An optoelectronic semiconductor chip includes a semiconductor body including a first semiconductor region and a second semiconductor region, a recess extending through the first semiconductor region, the recess having a bottom surface, where the second semiconductor region is exposed, and a blocking element arranged on the bottom surface, wherein the at least one recess has a first width and a second width parallel to the main extension plane of the semiconductor body, and the first width is smaller than the second width.Type: ApplicationFiled: January 22, 2019Publication date: July 25, 2019Inventors: Thomas Oszinda, Ban Loong Chris Ng
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Publication number: 20190019759Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.Type: ApplicationFiled: September 19, 2018Publication date: January 17, 2019Inventors: Sang Hoon AHN, Tae Soo KIM, Jong Min BAEK, Woo Kyung YOU, Thomas OSZINDA, Byung Hee KIM, Nae In LEE
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Patent number: 10128148Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.Type: GrantFiled: June 29, 2017Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Viet Ha Nguyen, Nae In Lee, Thomas Oszinda, Byung Hee Kim, Jong Min Baek, Tae Jin Yim
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Patent number: 10096549Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.Type: GrantFiled: April 5, 2017Date of Patent: October 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Byung Hee Kim, Thomas Oszinda, Deok Young Jung, Jong Min Baek, Tae Jin Yim
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Patent number: 9972528Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.Type: GrantFiled: December 9, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
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Publication number: 20180102280Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.Type: ApplicationFiled: June 29, 2017Publication date: April 12, 2018Inventors: Viet Ha NGUYEN, Nae In LEE, Thomas OSZINDA, Byung Hee KIM, Jong Min BAEK, Tae Jin YIM
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Patent number: 9929098Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.Type: GrantFiled: February 19, 2016Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Jin Yim, Sang-Hoon Ahn, Thomas Oszinda, Jong-Min Baek, Byung Hee Kim, Nae-In Lee, Kee-Young Jun
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Publication number: 20180076140Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.Type: ApplicationFiled: April 5, 2017Publication date: March 15, 2018Inventors: Byung Hee KIM, Thomas Oszinda, Deok Young Jung, Jong Min Baek, Tae Jin Yim
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Publication number: 20170213786Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.Type: ApplicationFiled: October 25, 2016Publication date: July 27, 2017Inventors: Sang Hoon AHN, Tae Soo KIM, Jong Min BAEK, Woo Kyung YOU, Thomas OSZINDA, Byung Hee KIM, Nae In LEE
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Publication number: 20170178949Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
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Patent number: 9666478Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.Type: GrantFiled: February 19, 2016Date of Patent: May 30, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Thomas Oszinda, Tae-Jin Yim, Sang-Hoon Ahn, Nae-In Lee
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Patent number: 9653400Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.Type: GrantFiled: December 30, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Yim, Woo-Kyung You, Jong-Min Baek, Sang-Hoon Ahn, Thomas Oszinda, Kee-Young Jun
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Patent number: 9576848Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.Type: GrantFiled: September 8, 2015Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Taejin Yim, Thomas Oszinda, Byunghee Kim, Sanghoon Ahn, Naein Lee, Keeyoung Jun
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Publication number: 20160329242Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.Type: ApplicationFiled: February 19, 2016Publication date: November 10, 2016Inventors: Thomas OSZINDA, Tae-Jin YIM, Sang-Hoon AHN, Nae-In LEE