Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

Abstract: In an approach to sharing memory between a first guest and a second guest both running on a data processing system, one or more computer processors provide a virtual device to a first guest for proxying memory accesses between the first guest and a second guest, where the first guest is associated with the second guest, and where the first guest is running a first operating system and the second guest is running a second operating system. The one or more computer processors send one or more device related functions to the second guest, wherein the virtual device enables sharing memory between the first guest and the second guest.

Abstract: In an approach to sharing memory between a first guest and a second guest both running on a data processing system, one or more computer processors provide a virtual device to a first guest for proxying memory accesses between the first guest and a second guest, where the first guest is associated with the second guest, and where the first guest is running a first operating system and the second guest is running a second operating system. The one or more computer processors send one or more device related functions to the second guest, wherein the virtual device enables sharing memory between the first guest and the second guest.

Abstract: In an approach to sharing memory between a first guest and a second guest both running on a data processing system, one or more computer processors provide a virtual device to a first guest for proxying memory accesses between the first guest and a second guest, where the first guest is associated with the second guest, and where the first guest is running a first operating system and the second guest is running a second operating system. The one or more computer processors send one or more device related functions to the second guest, wherein the virtual device enables sharing memory between the first guest and the second guest.

Abstract: In an approach to sharing memory between a first guest and a second guest both running on a data processing system, one or more computer processors provide a virtual device to a first guest for proxying memory accesses between the first guest and a second guest, where the first guest is associated with the second guest, and where the first guest is running a first operating system and the second guest is running a second operating system. The one or more computer processors send one or more device related functions to the second guest, wherein the virtual device enables sharing memory between the first guest and the second guest.

Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.