Abstract: A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board (62) that receives a unit (60) of the device is directly attached to a test head (16). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus (66) to a test head. A probe system (64) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.

Abstract: A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board (62) that receives a unit (60) of the device is directly attached to a test head (16). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus (66) to a test head. A probe system (64) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.

Abstract: A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel.