Abstract: A storage array and systems for configuring a storage array are provided. In one example, the storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect.

Abstract: A storage array and systems for configuring a storage array are provided. In one example, the storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect.

Abstract: A sled assembly for a storage array is disclosed. One example of the sled assembly includes a first rail extending between a first end and a second end and a second rail extending between the first end and the second end. The second rail is parallel to the first rail. Further included is an ejector body that is coupled to the first rail and the second rail at the first end. A first drive guide having a first pair of channels is provided. The first drive guide is disposed adjacent to and parallel to the first rail and interfaced with the ejector body at the first end. A second drive guide having a second pair of channels is further provided. The second drive guide is disposed adjacent to and parallel to the second rail and interfaced with the ejector body at the first end. A first drive and a second drive are configured to be disposed between the first rail and the second rail and respectively enabled to slide into and out of the sled assembly.

Abstract: A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.

Abstract: A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.

Abstract: A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.