Abstract: An apparatus includes a controllable delay circuit, a clock doubler circuit, a low-pass filter, and a comparator. The controllable delay circuit generates a delayed clock signal from a reference clock signal. The clock doubler circuit generates an output clock signal from the delayed clock signal. A frequency of the output clock signal is twice a frequency of the reference clock signal. The low-pass filter receives the output clock signal and generates a filtered signal. The comparator generates an output signal by comparing the filtered signal with a reference signal.