Patents by Inventor Thomas P. Thomas

Thomas P. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10374419
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas
  • Patent number: 9535865
    Abstract: An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Thomas P. Thomas, Randy B. Osborne, Rajesh Kumar
  • Patent number: 9519609
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Thomas P. Thomas, Rajesh Kumar
  • Patent number: 9384163
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas, Rajesh Kumar
  • Publication number: 20160164281
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas
  • Patent number: 9306390
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas
  • Patent number: 9143120
    Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Randy B. Osborne, Stanley S. Kulick, Erin Francom, Thomas P. Thomas
  • Patent number: 8902956
    Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Thomas P. Thomas, Stanley S. Kulick, Randy B. Osborne
  • Publication number: 20140204490
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 24, 2014
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas
  • Publication number: 20140201405
    Abstract: An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 17, 2014
    Inventors: Thomas P. Thomas, Randy B. Osborne, Rajesh Kumar
  • Patent number: 8736328
    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Thomas P. Thomas
  • Publication number: 20140089549
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
    Type: Application
    Filed: December 22, 2011
    Publication date: March 27, 2014
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas, Rajesh Kumar
  • Publication number: 20140009195
    Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.
    Type: Application
    Filed: December 22, 2011
    Publication date: January 9, 2014
    Inventors: Randy B. Osborne, Stanley S. Kulick, Erin Francom, Thomas P. Thomas
  • Publication number: 20130322556
    Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
    Type: Application
    Filed: December 22, 2011
    Publication date: December 5, 2013
    Inventors: Thomas P. Thomas, Stanley S. Kulick, Randy B. Osborne
  • Publication number: 20130318266
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Application
    Filed: December 22, 2011
    Publication date: November 28, 2013
    Inventors: Thomas P. Thomas, Rajesh Kumar
  • Publication number: 20130300475
    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.
    Type: Application
    Filed: December 22, 2011
    Publication date: November 14, 2013
    Inventors: Nasser A. Kurd, Thomas P. Thomas
  • Patent number: 7724078
    Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Chaodan Deng, Thomas P. Thomas
  • Publication number: 20080231352
    Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Nasser A. Kurd, Chaodan Deng, Thomas P. Thomas
  • Patent number: 7418163
    Abstract: An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: August 26, 2008
    Inventors: Kishore K. Chakravorty, Joseph F. Ahadian, Johanna Swan, Thomas P. Thomas, Brandon C. Barnett, Ian Young
  • Patent number: 7049704
    Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: May 23, 2006
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Johanna Swan, Brandon C. Barnett, Joseph F. Ahadian, Thomas P. Thomas, Ian Young