Patents by Inventor Thomas P. Wallace

Thomas P. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105716
    Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Sukru YEMENICIOGLU, Mohit K. HARAN, Stephen M. CEA, Charles H. WALLACE, Tahir GHANI, Shengsi LIU, Saurabh ACHARYA, Thomas O'BRIEN, Nidhi KHANDELWAL, Marie T. CONTE, Prabhjot LUTHRA
  • Publication number: 20240105803
    Abstract: Integrated circuit structures having trench contact depopulation structures, and methods of fabricating integrated circuit structures having trench contact depopulation structures, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate stack is over the vertical stack of horizontal nanowires. A dielectric trench structure is adjacent to the gate stack. A dielectric sidewall spacer is between the gate stack and the dielectric trench structure. A dielectric gate cut plug is extending through the gate stack, the dielectric sidewall spacer, and the dielectric trench structure.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Dan S. LAVRIC, Charles H. WALLACE, Tahir GHANI, Saurabh ACHARYA, Thomas O'BRIEN
  • Patent number: 6310185
    Abstract: The invention provides for the production of several humanized murine antibodies specific for the antigen Lewis Y, which is recognized by murine atibodies specific for the Lewis Y antigen. The Lewis Y antigen is expressed in normal tissues but the level of expression is higher in certain tumour types so that the antigen can be used as a marker for cells of some breast, colon, gastric, esophageal, pancreatic, duodenal, lung, bladder and renal carcinomas and gastric and islet cell neuroendocrine tumours. The invention also provides for numerous polynucleotide encoding humanized Lewis Y specific antibodies, expression vectors for producing humanized Lewis Y specific antibodies, and host cells for the recombinant production of the humanized antibodies. The invention also provides methods for detecting cancerous cells (in vitro and in vivo) using humanized Lewis Y specific antibodies. Additionally, the invention provides methods of treating cancer using humanized Lewis Y specific antibodies.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: October 30, 2001
    Assignee: Memorial Sloan Kettering Cancer Center
    Inventors: Thomas P. Wallace, Kathryn Lesley Armour, Francis Joseph Carr, Lloyd J. Old, Elisabeth Stockert, Sydney Welt, Kunio Kitamura, Pilar Garin-Chesa