Abstract: An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

Abstract: Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

Abstract: A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and then deferring the reporting of the transmission error. The method defers the reporting of the transmission error by saving a sequence number for the message and by setting a deferred error flag in a state saved for the flow. The method processes the deferred transmission error when it receives an acknowledgement that completes an immediately preceding message in the flow. When a positive acknowledgement is received, the deferred transmission error is reported. When a negative acknowledgement is received, the deferred transmission error is ignored and a remote error is reported.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor.

Abstract: Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer.

Abstract: A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets.

Abstract: Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

Abstract: A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor.

Abstract: A network adapter includes a bypass buffer with sufficient capacity to store a packet from an upstream neighboring adapter and to store at least one additional incoming packet as a local packet is sent. The adapter also includes control logic which monitors the bypass buffer to determine whether the adapter may send local data packets. A network may be formed of such network adapters linked through counterrotating rings. If the control logic determines that the bypass buffer has sufficient storage available to avoid overflow while the adapter sends the local packet, the adapter sends the local packet. The control logic may choose to send a local packet only if there is sufficient room available within the bypass buffer to store a packet the same size as the local packet which is to be sent, thereby insuring that the bypass buffer does not overflow before the adapter can resume transmitting data from the bypass buffer.

Abstract: A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and then deferring the reporting of the transmission error. The method defers the reporting of the transmission error by saving a sequence number for the message and by setting a deferred error flag in a state saved for the flow. The method processes the deferred transmission error when it receives an acknowledgement that completes an immediately preceding message in the flow. When a positive acknowledgement is received, the deferred transmission error is reported. When a negative acknowledgement is received, the deferred transmission error is ignored and a remote error is reported.

Abstract: Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer.

Abstract: A buffer management subsystem receives data from one or more source processes for transfer to one or more destination processes. The buffer management subsystem includes a buffer memory and a buffer pointer FIFO that associated with one of the destination process. The buffer pointer FIFO stores pointers to buffers in the buffer memory which are available to be used to store data from the source process(es) for transfer to the respective associated destination process. When data is received from a source process for transfer to a destination process, a buffer pointer is retrieved from the buffer pointer FIFO associated with the destination process and used in storing the data in the buffer pointed to by the buffer pointer. When the data is retrieved from the buffer for transfer to the destination process, the buffer pointer to the buffer is returned to the buffer pointer FIFO.

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: A method and apparatus for high speed signal path arbitration and transfer of a plurality of source signals to a destination signal path, is provided. An arbiter system includes an arbiter and a multiplexer. The multiplexer includes a plurality of n inputs each coupled to receive a source signal from one of a plurality of source signal paths and an output coupled to provide an output signal to the destination signal path. The multiplexer is controlled by a plurality of n select signal values received from the arbiter. The arbiter is coupled to receive a plurality of request signal values which prompt the arbiter to control the multiplexer to pass one of the source signals to the destination signal path. The multiplexer includes a plurality of n multiplexer signal paths each extending from one of n multiplexer inputs to the multiplexer output. Time characteristics of each of the n multiplexer signal paths are unequal.

Abstract: A computer has an AC power outlet, preferably a standard AC outlet, into which periperhal devices, such as video monitors, can be plugged. It can turn this outlet on and off under program control, preferably by writing an outlet control signal to an I/O port which controls the outlet. A activity monitor, preferably in software, generates outlet control signals when one or more of the computer's peripheral devices have been inactive for more than a predetermined time. In some embodiments, the activity monitor turn off different parts of the computer in response to different types of inactivity. Preferably the computer can turn off the AC outlet without turning off the computer as a whole, and preferably it turns off the AC power outlet when the computer is turned off. Normally the AC outlet and its switching circuitry are part of the computer's power supply.