Abstract: The present invention provides inducible chimeric cytokine receptors responsive to a ligand, e.g., a small molecule or protein, uses of such receptors for improving the functional activities of genetically modified immune cells, such as T cells, comprising the inducible chimeric cytokine receptors, and compositions comprising such cells.

Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.

Abstract: The disclosure provides CARs (CARs) that specifically bind to CD70. The disclosure further relates to engineered immune cells comprising such CARs, CAR-encoding nucleic acids, and methods of making such CARs, engineered immune cells, and nucleic acids. The disclosure further relates to therapeutic methods for use of these CARs and engineered immune cells comprising these CARs for the treatment of a condition associated with malignant cells expressing CD70 (e.g., cancer).

Abstract: An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

Abstract: Provided herein are systems, methods and computer readable storage media for facilitating payments for consumer transactions and redemption of deal offerings. In providing such functionality, the system can be configured to, for example, receive payment for one or more products, determine a deal voucher's current value and cause the redemption of the deal voucher.

Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

Abstract: A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.

Abstract: Aspects of the invention include techniques for providing a schema evolution on a live database system without an outage. A non-limiting example method includes initiating a schema change on a live database system. The schema change includes an attribute for a database object. A first application package having a user application that is dependent on the database object and that is bound with a release(deallocate) option is identified. Existing threads and new threads executing the first application package are routed to execute the first application package with a release(commit) option and the schema change on the live database system is completed. One or more additional threads concurrently executing one or more additional application packages remain executing with the release(deallocate) option.

Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

Abstract: Methods and systems are provided for managing a wagering system. In one exemplary embodiment, state information of a live event such as a sports game may be received in real time. During the event, a plurality of possible future states of the event and their associated probabilities (and odds) may be determined based on the state information, historical information, and current in-game information. A betting market is created for betting on the possible future states at determined odds. The betting market is closed and winning and losing bets are resolved based on updated state information.

Abstract: A light member includes a housing having an outer surface and an inner surface, a portion of the outer surface includes a lens. A light source is mounted in the housing. The light source is directed toward the lens. A plurality of light manipulating elements is arranged in the housing between the light source and the lens. Each of the plurality of light manipulating elements includes a body having a first side surface and a second side surface. Each of the first side surface and the second side surface is a light manipulating surface.

Abstract: The present disclosure provides a system and methods for time of flight imaging, comprising: (a) an imaging sensor configured to receive a plurality of light signals reflected from a surgical scene, wherein the imaging module comprises a first imaging unit configured for time of flight (TOF) imaging; a second imaging unit configured for at least one of laser speckle imaging and fluorescence imaging; and an optical element configured to (i) direct a first set of light signals to the first imaging unit and (ii) direct a second set of light signals to the second imaging unit; and (b) an image processing module operatively coupled to the first imaging unit and the second imaging unit, wherein the image processing module is configured to generate one or more images of the surgical scene based on the first set of light signals and the second set of light signals.

Abstract: Some embodiments may provide a method for a desired operating environment. A signal to place a vehicle in a designated mode corresponding to a desired operating environment may be received. The designated mode may include modifications to one or more default operating characteristics of the vehicle. The modifications may be while the vehicle is in parked mode and a vehicle access key associated with the vehicle is within proximity of the vehicle. In response to receiving the signal, characteristics of the vehicle to be modified in order to create the desired operating environment may be identified. The default operating characteristics may relate to lighting or displays controlled by the vehicle, sounds controlled by the vehicle, or a passive entry system of the vehicle. One or more settings of the vehicle to change the default operating characteristics of the vehicle while in the designated mode may be modified.

Abstract: The present invention relates to genetically modified B cells and their uses thereof, for example, for the treatment of a variety of diseases and disorders, including cancer, heart disease, inflammatory disease, muscle wasting disease, neurological disease, and the like. In certain embodiments, the invention relates to an isolated modified B cell (“CAR-B cell”), capable of expressing a chimeric receptor (“CAR-B receptor”), wherein said chimeric receptor comprises (a) an extracellular domain; (b) a transmembrane domain; and (c) a cytoplasmic domain that comprises at least one signaling domain. In various embodiments, the invention comprises an isolated modified B cell, wherein said B cell is capable of expressing and secreting a payload, wherein the payload is not naturally expressed in a B cell or is expressed at higher levels than is naturally expressed in a B cell. In various embodiments, the payload is an antibody or fragment thereof.

Abstract: Systems and methods are provided for determining a response to a query in a dialog. An entity extractor extracts rules and conditions associated with the query and determines a particular task. The disclosed technology generates a transformer-based dialog embedding by pre-training a transformer using dialog corpora including a plurality of tasks. A task-specific classifier generates a first set of candidate responses based on rules and conditions associated with the task. The transformer-based dialog embedding generates a second set of candidate responses to the query. The classifier accommodates changes made to a task by an interactive dialog editor as machine teaching. A response generator generates a response based on the first and second sets of candidate responses using an optimization function.

Abstract: Methods and systems are disclosed for improving dialog management for task-oriented dialog systems. The disclosed dialog builder leverages machine teaching processing to improve development of dialog managers. In this way, the dialog builder combines the strengths of both rule-based and machine-learned approaches to allow dialog authors to: (1) import a dialog graph developed using popular dialog composers, (2) convert the dialog graph to text-based training dialogs, (3) continuously improve the trained dialogs based on log dialogs, and (4) generate a corrected dialog for retraining the machine learning.