Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.

Abstract: In a selected area of a display defined by a polygon, magnifying is simulated. The selected area may be, for example, a circle simulating a magnifying glass. Textures are represented by texel coordinates U and V, which specify the location of color components within a set of image data. Within the area selected to appear magnified, the present invention perturbs the texel location selection to simulate an angle of refraction in the selected area and offset texel coordinates.

Abstract: An anti-aliasing system provides anti-aliasing at the edges of objects in a displayed or printed image without video artifacts or the need for an expensive anti-aliasing buffer. As geometric data is rasterized, the rasterizer identifies pixels on the edge of objects in the image being rendered. These pixels are then rendered at a higher resolution with a number of sub-pixels. The Z-buffer is signaled as to which pixels will require the additional, higher resolution data. The Z-buffer then dynamically allocates memory space in an additional memory unit to hold that additional sub-pixel data. A memory offset or address is provided in the Z-buffer to direct the memory controller to the appropriate address in the additional memory unit when the data in the additional memory unit is being blended to produce the data defining the corresponding main pixel which data is then stored in the Z-buffer.

Abstract: In a Java Virtual Machine in which information is gathered about what sections of code get used most frequently in an embedded application. This information comprises binary data which is saved into non-volatile random access memory (RAM). The binary data is compressed for storage. At a subsequent startup, the stored compressed data is retrieved and decompressed and written to a volatile memory.

Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.