Abstract: The application is directed to a method for treating or preventing vasculopathy comprising administrating to a subject in need thereof a pharmaceutical composition comprising mesenchymal precursor cells (MPCs) and a prostacyclin. Also provided a method for treating or preventing vasculopathy in a subject in need thereof, comprising administering to the subject a prostacyclin and a mesenchymal stem cell (MSC) or a MSC-conditioned culture medium or administering to the subject a MSC or a MSC-conditioned culture medium that has treated with prostacyclin. Pharmaceutical compositions suitable for such treatments are also provided.

Abstract: The current application is directed to a method for treating pulmonary arterial hypertension (PAH), comprising: providing isolated endothelial progenitor cells (EPCs); treating the EPCs with prostacyclin, wherein the treated EPCs exhibit a by perproliferative phenotype with enhanced angiogenic property; and administering a composition comprising the treated EPCs into a subject suffering from PAH.

Abstract: The present invention relates to compositions comprising a decellularized tissue. The present invention also provides an engineered three dimensional lung tissue exhibiting characteristics of a natural lung tissue. The engineered tissue is useful for the study of lung developmental biology and pathology as well as drug discovery.

Abstract: Provided are methods for treating or preventing vasculopathy in a subject in need thereof, comprising administering to the subject a prostacyclin and a mesenchymal stem cell (MSC) or a MSC-conditioned culture medium or administering to the subject a MSC or a MSC-conditioned culture medium that has treated with prostacyclin. Pharmaceutical compositions suitable for such treatments are also provided.

Abstract: The present invention relates to compositions comprising a decellularized tissue. The present invention also provides an engineered three dimensional lung tissue exhibiting characteristics of a natural lung tissue. The engineered tissue is useful for the study of lung developmental biology and pathology as well as drug discovery.

Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.

Abstract: A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each thread and decreases it each time the execution pipeline executes an instruction of the thread. The scheduler includes an instruction execution rate for each thread. The scheduler increases the virtual water level based on the requested rate per a predetermined number of clock cycles. The scheduler includes virtual water pressure parameters that define a set of virtual water pressure ranges over the height of the virtual water bucket. When a thread's virtual water level moves from one virtual water pressure range to the next higher range, the scheduler increases the instruction issue priority for the thread; conversely, when the level moves down, the scheduler decreases the instruction issue priority for the thread.

Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.

Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.

Abstract: A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.

Abstract: A microprocessor coupled to a system memory includes a load request signal that requests data be loaded from the system memory into the microprocessor in response to a load instruction. The load request signal includes a load virtual page address. The microprocessor also includes a prefetch request signal that requests a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction. The prefetch request signal includes a prefetch virtual page address.

Abstract: The present invention relates to the field of therapeutic use of proteins, genes and cells. More specifically the invention relates to therapy based on the biological function of a secreted therapeutic protein. NsG33, in particular for the treatment of disorders of the nervous system. NsG33 is a nerve survival and growth factor with antiapoptotic effects on a cell line with neuronal potential and with neuroprotective and/or neurogenesis effects on a neural precursor cell line and on primary striatal cultures. The invention also relates to novel bioactive NsG33 polypeptide fragments and the corresponding encoding DNA sequences.

Abstract: A surgical blade includes a handle with a recess sized to receive the proximal end of a blade assembly. The recess includes a notch as well as opposed facing distal ridges designed to engage elevated surfaces in the blade assembly to maintain the blade assembly and handle assembled. The blade assembly includes a blade portion and a fitting having a protrusion sized to be received in the proximal notch of the recess in the handle when the blade portion is assembled to the handle. The fitting also includes side faces having opposed elevated surfaces obliquely disposed so that they are engaged by the distal ridges within the handle recess. The fitting also includes an upwardly extending catch that engages a distal surface on the handle to assist in locking the blade assembly to the handle. The recess of the handle includes inner tapered surfaces.

Abstract: A microprocessor with multiple stream prefetch engines each executing a stream prefetch instruction to prefetch a complex data stream specified by the instruction in a manner synchronized with program execution of loads from the stream is provided. The stream prefetch engine stays at least a fetch-ahead distance (specified in the instruction) ahead of the program loads, which may randomly access the stream. The instruction specifies a level in the cache hierarchy to prefetch into, a locality indicator to specify the urgency and ephemerality of the stream, a stream prefetch priority, a TLB miss policy, a page fault miss policy, a protection violation policy, and a hysteresis value, specifying a minimum number of bytes to prefetch when the stream prefetch engine resumes prefetching. The memory subsystem includes a separate TLB for stream prefetches; or a joint TLB backing the stream prefetch TLB and load/store TLB; or a separate TLB for each prefetch engine.

Abstract: A microprocessor coupled to a system memory includes a load request signal that requests data be loaded from the system memory into the microprocessor in response to a load instruction. The load request signal includes a load virtual page address. The microprocessor also includes a prefetch request signal that requests a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction. The prefetch request signal includes a prefetch virtual page address. The microprocessor also includes a memory subsystem including a first translation look-aside buffer (TLB) that translates the load virtual page address into a load physical page address, and a second TLB that translates the prefetch virtual page address into a prefetch physical page address.

Abstract: A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.