Patents by Inventor Thomas Pflueger
Thomas Pflueger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230257196Abstract: A storage and retrieval unit having a carriage which can be moved along a linear guide arranged on a floor in a shelf aisle in the direction of an X axis and which supports a vertical mast which extends perpendicular to the X axis in the direction of a vertical Y axis. A load receiver is mounted by one end only on a support device and can be moved vertically to a shelf compartment along the mast together with the support device, and inserted in the direction of a Z axis running perpendicular to the X axis and perpendicular to the Y axis into a shelf compartment, and the pulled back out of the same. The load receiver is additionally pivotable about a pivot axis X1 running parallel to the X axis, such that it can be brought into a position inclined downward towards the floor.Type: ApplicationFiled: April 21, 2023Publication date: August 17, 2023Applicant: Dambach Lagersysteme GmbH & Co. KGInventors: Thomas PFLUEGER, Franz BRUTLER
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Patent number: 10902348Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: GrantFiled: May 19, 2017Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Patent number: 10901745Abstract: A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.Type: GrantFiled: July 10, 2018Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Cedric Lichtenau, Peter Altevogt, Thomas Pflueger
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Patent number: 10896386Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: GrantFiled: November 3, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Patent number: 10754773Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.Type: GrantFiled: October 11, 2017Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Andreea Anghel, Cedric Lichtenau, Gero Dittmann, Peter Altevogt, Thomas Pflueger
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Patent number: 10684861Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: GrantFiled: September 25, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Patent number: 10649781Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: GrantFiled: December 15, 2017Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Publication number: 20200019407Abstract: A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Cedric Lichtenau, Peter Altevogt, Thomas Pflueger
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Patent number: 10528354Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.Type: GrantFiled: March 10, 2016Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
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Patent number: 10303481Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.Type: GrantFiled: December 2, 2015Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
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Publication number: 20190108123Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Inventors: Andreea Anghel, Cedric Lichtenau, Gero Dittmann, Peter Altevogt, Thomas Pflueger
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Publication number: 20190095214Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: ApplicationFiled: December 15, 2017Publication date: March 28, 2019Inventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Publication number: 20190095213Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Publication number: 20180336492Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: ApplicationFiled: November 3, 2017Publication date: November 22, 2018Inventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Publication number: 20180336491Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Inventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Patent number: 9779258Abstract: Secure extraction of state information of a computer system is provided. A method includes obtaining, by a security engine of a system, a public encryption key associated with a private decryption key; generating an extraction key that is inaccessible outside of the security engine; encrypting the extraction key with the public encryption key, to thereby obtain an encrypted extraction key; collecting state information of the system; encrypting the collected state information with the extraction key and storing the encrypted collected state information; and based on a request for access to the stored encrypted collected state information by a request for the extraction key, providing the extraction key to facilitate decryption of the stored encrypted state information.Type: GrantFiled: October 28, 2015Date of Patent: October 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Hall, Andreas Koenig, Cedric Lichtenau, Elaine Rivette Palmer, Thomas Pflueger, Peter A. Sandon
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Publication number: 20170161078Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.Type: ApplicationFiled: March 10, 2016Publication date: June 8, 2017Inventors: PETER ALTEVOGT, CEDRIC LICHTENAU, THOMAS PFLUEGER
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Publication number: 20170161077Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Inventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
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Patent number: 9336392Abstract: Secure initialization of the state of an electronic circuit. A processor determines the trusted state of one or more architecture state registers of an intellectual property core. The processor clears entries in a memory of the intellectual property core. The processor verifies that state machines, included in execution logic of the intellectual property core, have not generated output.Type: GrantFiled: September 17, 2015Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Cedric Lichtenau, Martin Padeffke, Thomas Pflueger, Hagen Schmidt
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Patent number: 9336391Abstract: Secure initialization of the state of an electronic circuit. A processor determines the trusted state of one or more architecture state registers of an intellectual property core. The processor clears entries in a memory of the intellectual property core. The processor verifies that state machines, included in execution logic of the intellectual property core, have not generated output.Type: GrantFiled: June 17, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Cedric Lichtenau, Martin Padeffke, Thomas Pflueger, Hagen Schmidt