Abstract: Embodiments of the present invention are directed to controlling device access fairness in frame-based switches by automatically and continuously counting the number of actively communicating devices connected to each port and the type of devices connected to each port, and adjusting fairness accordingly. During a sampling window, the number of active devices and the type of devices connected to each port is determined. At the start of each fairness window, a weighted number of slots are assigned to each port based on the number of active devices connected to each port and the type of devices connected to that port. Within a single fairness window, each port is able to provide device accesses to the frame-based switch in accordance with the number of slots assigned to that port.

Abstract: The use of routing logic within a single ASIC to save space, along with a way to modify and/or supplement the routing logic after the ASIC has been fabricated is disclosed. This is accomplished by providing a programmable “detour” or external router interface to allow for off-chip state machine portions or other external routing logic to be accessed. With this external router interface, additional routing modes or features that were not planned before the release of the ASIC can be implemented after release. The on-chip centralized routing logic may operate on incoming frames, and selectively operate on certain areas in the header to make the route. The off-chip state machine portions can complement the on-chip routing logic by working with the on-chip router, or replace certain portions of it.