Patents by Inventor Thomas Pompl

Thomas Pompl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240210466
    Abstract: This disclosure describes systems, methods, and devices related to testing an integrated circuit for defects. A method may include applying a nominal voltage to the integrated circuit for a first time period; applying a dynamic voltage greater than the nominal voltage to the integrated circuit for a second time period after the first time period; applying a static voltage greater than the dynamic voltage to the integrated circuit for a third time period after the second time period, wherein the static voltage is a target static voltage less than a target voltage; and applying the dynamic voltage to the integrated circuit during a fourth time period after the third time period.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Andres MALDONADO, Steve HERNDON, Thomas POMPL
  • Patent number: 7403026
    Abstract: The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: July 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Martin Kerber, Thomas Pompl
  • Publication number: 20060282725
    Abstract: The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.
    Type: Application
    Filed: March 16, 2006
    Publication date: December 14, 2006
    Inventors: Martin Kerber, Thomas Pompl
  • Patent number: 6730607
    Abstract: A method of fabricating a barrier layer includes oxidizing a silicon-containing substrate to form a substrate oxide layer on the surface of the substrate, producing an oxygen-impervious layer at an interface between the substrate oxide layer and the substrate, and etching the substrate oxide layer until the underlying oxygen-impervious layer is uncovered.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 4, 2004
    Assignee: Infineon Technologies AG
    Inventors: Helmut Wurzer, Martin Schrems, Anke Krasemann, Thomas Pompl
  • Publication number: 20020068465
    Abstract: The capacitive electrode structure has a semiconductor substrate, a metal oxide layer on the semiconductor substrate, an oxidation inhibiting layer on the metal oxide layer, and an electrode formed on the oxidation inhibiting layer. The oxidation inhibiting layer is substantially impervious to oxygen and prevents oxygen atoms from diffusing into the metal oxide layer.
    Type: Application
    Filed: December 4, 2000
    Publication date: June 6, 2002
    Inventors: Anke Krasemann, Thomas Pompl, Martin Schrems, Helmut Wurzer
  • Publication number: 20020055269
    Abstract: Method for fabricating a barrier layer having the following steps, namely
    Type: Application
    Filed: June 15, 2001
    Publication date: May 9, 2002
    Inventors: Helmut Wurzer, Martin Schrems, Anke Krasemann, Thomas Pompl
  • Publication number: 20010046787
    Abstract: The present invention provides a method for forming a dielectric 1; 7, 8 on a semiconductor substrate 2 having the following steps: implantation of ions into a surface layer of the semiconductor substrate 2, the ions forming a first dielectric layer 7; and performance of a thermal oxidation process for forming a second dielectric layer 8 on the first dielectric layer 7. Consequently, e.g. by the implantation of nitrogen ions into a surface layer of a silicon substrate, the imperfection density of the dielectric formed can be reduced approximately by a factor of 10.
    Type: Application
    Filed: April 18, 2001
    Publication date: November 29, 2001
    Inventors: Martin Kerber, Helmut Wurzer, Thomas Pompl