Abstract: A method and system for extrapolating a sampling rate from received digital cells in an integrated services hub in residential or business telecommunication systems. The system is implemented by a CPU controlling the hub operations. An input buffer is implemented by the CPU and its RAM. The CPU generates a fill level indicating the relative capacity of the buffer that is filled with samples not yet coupled to a CODEC. The CPU produces a divisor based on the fill level. A baud rate generator in the CPU uses the CPU local clock and the divisor to produce a sample rate at which buffer samples are coupled to the CODEC. The divisor is adjusted to maintain the fill level within a desired range. The sample rate is also used to sample analog signals coupled to the CODEC.

Abstract: The present invention discloses a method and apparatus for preventing contention on a common data bus between a CPU and a peripheral device with which the CPU exchanges data. A transceiver with bus hold is used to connect the bus connections of the CPU and peripheral. Control logic receives a CPU data strobe signal and generates control signals for the transceiver and the peripheral. After these control signals go inactive, the peripheral outputs transition to the high impedance state and the bus hold circuits maintain the last peripheral output data valid for reading by the CPU at the end of its read cycle. As soon as the CPU goes to a write cycle and drives the data bus, the bus hold circuits automatically switch to follow the new data.

Abstract: The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known reference clock for a digital signal processor. A first counter counts the reference clock cycles during the same time period in which a second counter counts the processor clock cycles. The number of processor clock cycles counted is divided by the number of reference clock cycles counted and the result is multiplied by the frequency of the reference clock. The calculated processor clock frequency is compared to a table of available CPU clock speeds and the closest available clock speed is selected. The selected available clock speed is then stored as a variable in RAM for use by all software which uses the processor clock as a base for generating absolute timing signals, such as a one second clock.

Abstract: An integrated access device (IAD) provides a broadband communication link between a home phoneline networking alliance (HPNA) local area network (LAN) and an external network, to form a wide area network (WAN). The HPNA LAN includes a plurality of personal computers each coupled to a first building telephone line through an HPNA port. In one embodiment, the IAD includes an HPNA interface, a first processor, a memory subsystem and a wireless interface. The HPNA interface is coupled to the HPNA LAN and the first processor, which is coupled to the memory subsystem that is utilized for storing information. The wireless interface is also coupled to the first processor and provides a communication link between the IAD and the external network.

Abstract: An integrated services digital network (ISDN) private exchange device is provided, which includes connectors for connection to an ISDN local exchange, a plurality of ports for connection to respective analog telephone devices, a plurality of ports for connection to respective digital devices, and an ISDN digital port for connection to at least one additional ISDN terminal device. The private exchange device may include a pair of ports for connection to two different analog telephone devices, each having simultaneous access capability with the ISDN network. Further, the private exchange device may include four ports for connection up to four digital devices, which are each capable of simultaneously accessing the ISDN local exchange. The ISDN digital port can be connected with up to eight ISDN terminals or terminal adapters.