Abstract: A process for designing CMOS integrated circuits which prevents electrostatic charges from damaging a gate of a connected transistor. Once the routing of a metallic conductors for the integrated circuit is defined, a determination is made whether or not a conductor connects to the gate of a transistor and violates an antenna rule. A metallic conductor involved in an identified violation is traced along its length for a location on an adjacent layer which is free of metallic conductors. The metallic conductor is segmented at the location providing a split conductor having spaced apart ends. Subsequent processing of the layer avoids the accumulation of excessive charge on the split conductor. The first and second segments are reconnected during processing of the adjacent metalization layer through via holes connected to the spaced apart segments.