Abstract: A method of operating a data processing system to operate a first instrument and a second instrument connected to the data processing system is disclosed. The method includes displaying a measurement table. The data processing system receives user input defining a first parameter that is to be varied during a testing procedure by the first instrument and a first measurement to be made by the second instrument during the test procedure, a plurality of first parameter values to be used in the testing procedure. The data processing system causes the first instrument to provide each of the first parameter values and the second instrument to make the measurement and enter the measurement in a corresponding cell of a second row in the measurement table when the first instrument provides each of the first parameter values.

Abstract: A test sequencer software application and method for management and execution of sequence items. The test sequencer software application includes a management module and an execution module. The management module has capabilities of obtaining multiple sequence items definitions, of obtaining configuration information, of creating multiple lists of ordered sequence items from the sequence items definitions, and of separately linking each list of sequence items to one of multiple sequence engines from the configuration information. The execution module includes a sequencer controller module and the multiple sequence engines. The sequence controller module activates each of the multiple sequence engines in a preselected order and each sequence engine executes the ordered sequence items in each list linked to that sequence engine.

Abstract: In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are also determined for the tests, as are the instruments needed to execute the tests. Then, in response to the test execution times, the test dependencies, and the instruments needed to execute the plurality of tests, a plurality of different and synchronized test execution orders for the plurality of tests are developed. Each of the test execution orders specifies a sequence of tests that is to be executed for one of a plurality of UUTs that are to be tested in parallel; and, typically, the plurality of different test execution orders will be constrained to develop different test execution orders that optimize a total time to test the plurality of UUTs, a usage cost of instruments used to test the plurality of UUTs, or both. Other embodiments are also disclosed.

Abstract: In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are also determined for the tests, as are the instruments needed to execute the tests. Then, in response to the test execution times, the test dependencies, and the instruments needed to execute the plurality of tests, a plurality of different and synchronized test execution orders for the plurality of tests are developed. Each of the test execution orders specifies a sequence of tests that is to be executed for one of a plurality of UUTs that are to be tested in parallel; and, typically, the plurality of different test execution orders will be constrained to develop different test execution orders that optimize a total time to test the plurality of UUTs, a usage cost of instruments used to test the plurality of UUTs, or both. Other embodiments are also disclosed.

Abstract: The present invention is a method and instrument for testing a device. The device under test (DUT) may be an electronic device, circuit, PCB, or product. The present invention compares events measured on a known good DUT with events measured on a potentially faulty DUT. Events on the DUT may be stimulated by injecting one or more input signals into the DUT. Events are observed and measured at signal nodes termed “observation nodes.” Events at the observation nodes are recorded and compiled into event lists. Event lists for a potentially faulty DUT are time aligned and compared with event lists for a known good DUT to determine whether the potentially faulty DUT is or is not actually faulty. The present invention can intelligently adapt the selection of observation nodes, on the basis of information about a DUT, to produce the most useful event lists for comparison.

Abstract: A method and apparatus are disclosed for reducing the likelihood of damage to digital logic devices under test or located in close electrical proximity to the device under test while attempting to locate faults in circuit assemblies using digital incircuit test techniques.