Patents by Inventor Thomas R. Glass

Thomas R. Glass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170336402
    Abstract: What has been developed is an improved method of determining the binding constants between two molecules that requires significantly fewer materials and potentially less time (in the case of a whole cell analysis less time to grow cell cultures as fewer cells are required in the same analysis) to undertake. The method involves utilizing an NSB measurement in preferably an n-curve analysis in order to determine the Kd and/or Rt without having to complete actual measurements to determine the lower knee of the curve(s) in the n-curve analysis. Preparing the experiment utilizing the additional samples allows an experiment represented in a binding curve having an upper and a lower knee to no longer be required to run through the lower knee to a point of completion.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: STEVE J. LACKIE, THOMAS R. GLASS
  • Publication number: 20160195518
    Abstract: The present disclosure is directed toward improved methods of conducting a competitive binding assay or experiment. The methodology includes utilizing either a positive control, a negative control, or both in order to scale experimentation results to results that can be utilized to obtain a precise measurement of the kinetic rate constant (the off rate denoted as koff) describing the dissociation of a non-covalent complex such as an antibody antigen complex, receptor ligand complex, etc.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: Thomas R. Glass, Steve J. Lackie
  • Publication number: 20090294878
    Abstract: The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
    Type: Application
    Filed: August 7, 2009
    Publication date: December 3, 2009
    Inventors: Zhiping Yin, Ravi Iyer, Thomas R. Glass, Richard Holscher, Ardavan Niroomand, Linda K. Somerville, Gurtej S. Sandhu
  • Patent number: 7576400
    Abstract: The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: August 18, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Zhiping Yin, Ravi Iyer, Thomas R. Glass, Richard Holscher, Ardavan Niroomand, Linda K. Somerville, Gurtej S. Sandhu
  • Patent number: 7387866
    Abstract: A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Thomas R. Glass, Gurtej Sandhu
  • Patent number: 7315074
    Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: January 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Zhiping Yin, Thomas R. Glass, Kunal R. Parekh, Gurtej Singh Sandhu
  • Patent number: 7250247
    Abstract: A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Thomas R. Glass, Gurtej Sandhu
  • Patent number: 7167156
    Abstract: The present invention comprises construction of a display from display elements that are actuated using the physical principle of electrowetting. In one embodiment, pores within porous silicon are filled with an ionic and an optically reflective electronic conductor, and actuated by application of an electric potential across the pore. An image is then formed on an array of such pores by applying an appropriate voltage to each pore of the array to create an optical image in the light reflected off the electronic conductors. Such a display may be constructed to have very high resolution, making it desirable for creating real-time holographic images, or for creating high-resolution mask images for use in photolithography.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Thomas R. Glass
  • Patent number: 7091050
    Abstract: The present invention provides an improved system for detecting the presence or level of an analyte in a sample. In “competition-like” assays of the present invention, a sample including an analyte is mixed with a second ligand to which the analyte binds, and the mixture is exposed to a solid phase containing a first ligand that can compete with the analyte for binding to the second ligand. According to the present invention, the time of exposure of the mixture to the solid phase is limited so that substantially no dissociation of analyte/second ligand complex occurs. The competition-like assays of the present invention are preferably performed with a solid phase containing a substantial excess of first ligand. In “sandwich-type” assays of the present invention, a sample including an analyte is contacted with a solid phase including a first ligand that binds the analyte and, simultaneously or subsequently, is contacted with a second ligand that binds the analyte (or the analyte/first ligand complex).
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: August 15, 2006
    Assignee: Sapidyne Instruments Inc.
    Inventors: Steve J. Lackie, Thomas R. Glass
  • Patent number: 6900515
    Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: May 31, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Zhiping Yin, Thomas R. Glass, Kunal R. Parekh, Gurtej Singh Sandhu
  • Publication number: 20040132215
    Abstract: The invention comprises methods of detecting the presence or level of an analyte in a sample by detecting the formation of a binding complex on a solid phase.
    Type: Application
    Filed: October 22, 2003
    Publication date: July 8, 2004
    Inventors: Steve J. Lackie, Thomas R. Glass
  • Patent number: 6664114
    Abstract: The present invention provides an improved system for detecting the presence or level of an analyte in a sample. In “competition-like” assays of the present invention, a sample including an analyte is mixed with a second ligand to which the analyte binds, and the mixture is exposed to a solid phase containing a first ligand that can compete with the analyte for binding to the second ligand. According to the present invention, the time of exposure of the mixture to the solid phase is limited so that substantially no dissociation of analyte/second ligand complex occurs. The competition-like assays of the present invention are preferably performed with a solid phase containing a substantial excess of first ligand.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: December 16, 2003
    Assignee: Sapidyne Instruments, Inc.
    Inventors: Steve J. Lackie, Thomas R. Glass
  • Publication number: 20030155626
    Abstract: A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.
    Type: Application
    Filed: March 14, 2003
    Publication date: August 21, 2003
    Inventors: Philip J. Ireland, Thomas R. Glass, Gurtej Sandhu
  • Patent number: 6605502
    Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: August 12, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Steven M. McDonald, Thomas R. Glass, Zhiping Yin
  • Patent number: 6495450
    Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: December 17, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Steven M. McDonald, Thomas R. Glass, Zhiping Yin
  • Publication number: 20020179990
    Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
    Type: Application
    Filed: July 22, 2002
    Publication date: December 5, 2002
    Applicant: Micron Technology, Inc.
    Inventors: Mark Fischer, Zhiping Yin, Thomas R. Glass, Kunal R. Parekh, Gurtej Singh Sandhu
  • Publication number: 20020155698
    Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.
    Type: Application
    Filed: June 17, 2002
    Publication date: October 24, 2002
    Applicant: Micron Technologies, Inc.
    Inventors: Ravi Lyer, Steven M. McDonald, Thomas R. Glass, Zhiping Yin
  • Patent number: 6461950
    Abstract: In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: October 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Zhiping Yin, Ravi Iyer, Thomas R. Glass, Richard Holscher, Ardavan Niroomand, Linda K. Somerville, Gurtej S. Sandhu
  • Patent number: 6423582
    Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Zhiping Yin, Thomas R. Glass, Kunal R. Parekh, Gurtej Singh Sandhu
  • Patent number: 6423631
    Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Steven M. McDonald, Thomas R. Glass, Zhiping Yin