Patents by Inventor Thomas R. Huff

Thomas R. Huff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10282296
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, David Papworth, James D. Allen
  • Publication number: 20190012266
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Publication number: 20180165199
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 7216138
    Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, legal representative, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar, Hsien-Cheng E. Hsieh, deceased
  • Publication number: 20040268094
    Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format.
    Type: Application
    Filed: February 14, 2001
    Publication date: December 30, 2004
    Inventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Publication number: 20030177312
    Abstract: In an out-of-order execution computer system, a fast store forwarding buffer (FSFB) is conditionally signaled to output buffered store data of buffered memory store instructions to fill a buffered memory load instruction. The FSFB is coupled to a rotator so that the store data can be rotated from a first position to a second position. A control unit coupled with the FSFB determines whether or not to signal the FSFB to forward the store data. The control unit is also coupled with the rotator to signal the rotator whether and by how much to rotate the forwarded store data. The control unit is configured to detect a number of dependencies between a buffered memory load instruction and one or more buffered memory store instructions.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 18, 2003
    Inventors: Aravindh Baktha, Michael D. Upton, Thomas R. Huff
  • Patent number: 6502115
    Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: December 31, 2002
    Assignee: Intel Corporation
    Inventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6480868
    Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: November 12, 2002
    Assignee: Intel Corporation
    Inventors: Mohammad A.F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Publication number: 20010023480
    Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.
    Type: Application
    Filed: April 27, 2001
    Publication date: September 20, 2001
    Inventors: Mohammad A.F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6292815
    Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: September 18, 2001
    Assignee: Intel Corporation
    Inventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Publication number: 20010016902
    Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
    Type: Application
    Filed: April 27, 2001
    Publication date: August 23, 2001
    Inventors: Mohammad A.F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6266769
    Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: July 24, 2001
    Assignee: Intel Corporation
    Inventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6263426
    Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: July 17, 2001
    Assignee: Intel Corporation
    Inventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6247116
    Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 16-bit number in the integer format. The 16-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: June 12, 2001
    Assignee: Intel Corporation
    Inventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 6185670
    Abstract: A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which fetches instructions to be executed by the processor. An instruction may conform to an instruction format which includes a number of fields that specify an operation class code, an operation selector code, and one or more operands. The processor also contains a decoder which uses the operation class code to generate a single execution flow that is capable of executing a class of similar operations. The single execution flow, in the form of execution control information, is sent to an execution unit along with the associated operands. The operation selector code is also passed to the execution unit. The execution unit performs the specific operation identified by the operation selector code and execution control information.
    Type: Grant
    Filed: October 12, 1998
    Date of Patent: February 6, 2001
    Assignee: Intel Corporation
    Inventors: Thomas R. Huff, Shreekant S. Thakkar, Roger A. Golliver
  • Patent number: 6052769
    Abstract: A method comprises decoding a single instruction having a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. Each of the plurality of byte masks identified by the second operand of the single decoded instruction are analyzed, wherein select bytes of the plurality of bytes identified by the first operand are moved to an implicitly defined location based, at least in part, on the analysis of the individual byte masks identified by the second operand of the single decoded instruction.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: April 18, 2000
    Assignee: Intel Corporation
    Inventors: Thomas R. Huff, Shreekant Thakkar, Nathaniel Hoffman
  • Patent number: 5995122
    Abstract: A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: November 30, 1999
    Assignee: Intel Corporation
    Inventors: Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar