Abstract: A method of fabricating a neutron detection structure includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer where at least a portion of the first substrate was removed, permanently bonding a second substrate to the conversion layer, removing the carrier, and providing at least one electrical contact to the device layer. A method of fabricating a neutron detection structure, corresponding to an alternate embodiment, includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer onto a second substrate, permanently bonding the coated substrate where at least a portion of the first substrate was removed, removing the carrier, and providing at least one electrical contact to the device layer.

Abstract: A neutron detection structure built from a Silicon-On-Insulator memory cell includes a conversion layer for converting incident neutrons into emitted charged particles, a device layer for receiving the emitted charged particles, a buried oxide layer separating the conversion layer from the device layer and directly adjacent to the conversion layer and the device layer, an isolation layer, a passivation layer formed on the isolation layer opposite the device layer and buried oxide layer, a carrier adhered by an adhesion layer to the passivation layer opposite the isolation layer, and a plurality of conductive contacts to provide electrical contact to the device layer.

Abstract: A method of fabricating a neutron detection structure includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer where at least a portion of the first substrate was removed, permanently bonding a second substrate to the conversion layer, removing the carrier, and providing at least one electrical contact to the device layer. A method of fabricating a neutron detection structure, corresponding to an alternate embodiment, includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer onto a second substrate, permanently bonding the coated substrate where at least a portion of the first substrate was removed, removing the carrier, and providing at least one electrical contact to the device layer.

Abstract: A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes.

Abstract: An optical device can be fabricated by forming a silicon rib, such as a poly-silicon rib, on a SOI substrate so that a portion of the SOI substrate is exposed, and by forming silicon spacers, such as amorphous or poly-silicon spacers, that round off corners of the silicon rib.

Abstract: A neutron detection structure built from a Silicon-On-Insulator memory cell includes a conversion layer for converting incident neutrons into emitted charged particles, a device layer for receiving the emitted charged particles, a buried oxide layer separating the conversion layer from the device layer and directly adjacent to the conversion layer and the device layer, an isolation layer, a passivation layer formed on the isolation layer opposite the device layer and buried oxide layer, a carrier adhered by an adhesion layer to the passivation layer opposite the isolation layer, and a plurality of conductive contacts to provide electrical contact to the device layer.

Abstract: A semiconductor device has a silicon layer and a first dielectric layer. A transistor has a drain and a source that are at least partially in the silicon layer. The transistor further has a gate and a spacer defining the gate. The first dielectric layer forms the spacer. A capacitor has first and second electrodes, the first electrode is formed at least partially in the silicon layer, and the first dielectric layer provides a dielectric for the capacitor between the first and second electrodes. A resistor has a resistive region formed at least partially in the silicon layer and has first and second resistor contact areas defined by the first dielectric layer. A second dielectric layer electrically isolates the transistor, the capacitor, and the resistor from conductive lines.

Abstract: A semiconductor device has a silicon layer and a first dielectric layer. A transistor has a drain and a source that are at least partially in the silicon layer. The transistor further has a gate and a spacer defining the gate. The first dielectric layer forms the spacer. A capacitor has first and second electrodes, the first electrode is formed at least partially in the silicon layer, and the first dielectric layer provides a dielectric for the capacitor between the first and second electrodes. A resistor has a resistive region formed at least partially in the silicon layer and has first and second resistor contact areas defined by the first dielectric layer. A second dielectric layer electrically isolates the transistor, the capacitor, and the resistor from conductive lines.

Abstract: An electroluminescent device in accordance with the present invention includes a device layer including devices for activating a plurality of pixel electrodes. The pixel electrodes are used for stimulating light emission from an electroluminescent stack disposed thereon. The plurality of pixel electrodes have an upper surface facing in a first direction. An interconnection system is disposed between the device layer and the plurality of pixel electrodes for coupling the devices to the pixel electrodes. The upper surface of the pixel electrodes includes a reflective material for reflecting the light emissions from the electroluminescent layer in the first direction.

Abstract: An electroluminescent device in accordance with the present invention includes a plurality of pixel electrodes disposed on a dielectric layer and coupled to control circuitry. An electroluminescent stack and a transparent electrode are included wherein the electroluminescent stack is disposed between the transparent electrode and the plurality of pixel electrodes. A plurality of guides are disposed between each of the pixel electrodes for guiding light from the electroluminescent stack when the pixel electrodes are activated by the control circuitry and reducing internal reflections of light within the electroluminescent stack. Another device and method include a dielectric layer disposed between the pixel electrodes for absorbing light and reducing a threshold voltage of the stack.

Abstract: An active matrix electroluminescent display having an array of pixel electrodes disposed on a transparent substrate. Each pixel electrode having an associated electronic circuit formed intermediate the pixel electrode and the transparent substrate to which it is electrically connected. The array of pixel electrodes are overlayed with an electroluminescent stack and a transparent ITO conductive layer. The surface of each pixel electrode is uniformly texturized to enhance the brightness of the pixel element when it is activated to its luminous state by its associated electronic circuit.