Abstract: Methods of treating or preventing diseases caused by viral infections via the administration of pyronaridine, quinacrine, and/or tilorone are described. The viral infections can be caused by viruses such as Marburg virus (MARV), Chikungunya virus (CHIKV), norovirus, Middle East Respiratory Syndrome coronavirus (MERS-CoV), and Nipah virus.

Abstract: Methods of treating or preventing diseases caused by viral infections via the administration of pyronaridine, quinacrine, and/or tilorone are described. The viral infections can be caused by viruses such as Marburg virus (MARV), Chikungunya virus (CHIKV), norovirus, Middle East Respiratory Syndrome coronavirus (MERS-CoV), and Nipah virus.

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic.

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic.

Abstract: A computer system has both positive decode agents and subtractive decode agents that are targets of bus transactions, as well as an agent that does not perform a positive decode of a bus transaction, yet does claim bus transactions on behalf of agents to whom a bus transaction is directed.

Abstract: A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.