Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: The invention is related to identification of an interferon-analog (IFNL4) protein and genetic association with spontaneous clearance of HCV infection and response to treatment for HCV infection.

Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

Abstract: A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

Abstract: A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.