Abstract: An article of manufacture which has a substrate including electrical leads and bond pads electrically connected to the leads. Two or more integrated circuit semiconductor chips are supported on the substrate. Each of the chips includes a plurality of edges and a plurality of input/output (I/O) bond pads. A portion of the bond pads on each chip are located adjacent at least one edge of the respective chip. At least two separate sections of Tape Automated Bonding (TAB) tape electrically connect the I/O bond pads on each chip to the bond pads on the substrate. In a refinement of the invention, the sections of TAB tape each include a plurality of inner lead bond leads extending from a longitudinal (along the tape length) edge of the tape. Each inner lead bond is connectable to one of the I/O bond pads on the chips.

Abstract: A method and apparatus for forming a conductive bump on a metal or other conductive surface or layer. A substrate is provided which includes the metal surface, a passivation layer next to the metal surface and an etch stop layer next to the passivation layer. The etch stop and passivation layers have a via therethrough which exposes a portion of the metal surface. At least one sacrificial layer is formed next to the etch stop layer. Each sacrificial layer has a via therethrough which has a larger diameter than, and which is essentially aligned with, the via in the layer located (i) next to the sacrificial layer and (ii) closer to the metal surface. The vias are filled with a conductive paste which is allowed to cure or harden. The sacrificial layer(s) is(are) removed to expose the bump.

Abstract: A large electrode bump is generated on a substrate such as a circuit board. A small electrode bump is then formed on the large bump. Preferably a barrier layer is deposited over the large bump prior to formation of the small bump. In this case the small bump is formed on the barrier layer over the large bump. In one embodiment, the small bump is formed by applying a sacrificial layer on the large bump. A window is created in the sacrificial layer. A spring may optionally be inserted in the window. The window is then filled with a conductive material. Finally, the sacrificial layer is removed to reveal the small bump. In another embodiment, a small bump is formed on a semiconductor die and a larger bump is formed on a substrate. The semiconductor die is mounted on the substrate such that the bump on the die contacts the larger bump.

Abstract: A method of forming a conductive electrode bump on a first side of a dielectric substrate. The electrode bump is located such that it is in electrical contact with one end of an electrically conductive via passing through the substrate. An electrically conductive test pad, located on a second side of the substrate, is in electrical contact with the opposite end of the via. The method includes the steps of (a)forming a layer of conductive material of generally uniform thickness onto the first side of the substrate, the layer being in a routing pattern for routing electrical signals along the first side; and (b)selectively reducing the thickness of the layer in locations defining the routing pattern to a greater extent than in the location of the bump to provide a bump, that extends from the first side at a height greater than the routing pattern.

Abstract: An assembly of multiple quantities of solid state memory modules, built upon a high density interconnect substrate, is described. Each memory module is of itself constructed from a multiple number of separate bare solid state memory die appropriate to the function. A multiplicity of the memory modules are constructed on a single substrate, and thereupon each module is separated from the single substrate. The separate memory die are mounted to the surface of the high density substrate, which provides the interconnection necessary to complete the memory function. The high density substrate also provides the capability for close attached capacitors for signal filtering, test vias for optimal module test and thermal vias as appropriate. The provision for multiple memory modules enables economical manufacturing plus capability for systems level interconnect.

Abstract: A method and article made by such method are described for connecting electrodes on one face of an integrated circuit semiconductor device with those on a supporting substrate. The method comprises positioning electrodes formed on one face of the device into engagement with electrodes formed on the substrate. A force is applied to press the electrodes together and during application of the force a first adhesive is applied along only a minor portion of two edges of the device. The first adhesive is stiffened to provide a temporary connection of the device and the substrate. A mass of a second adhesive is applied over a face of said device opposite said one face and onto portions of the substrate adjacent the periphery of the device with substantially no adhesive located between the one face of the device and the substrate at a center area of the one face. The second adhesive is hardened to form an adhesive dome that permanently connects the device to the substrate.