Patents by Inventor Thomas R. Puzak

Thomas R. Puzak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10338923
    Abstract: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip G. Emma, Allan M. Hartstein, Keith N. Langston, Brian R. Prasky, Thomas R. Puzak, Charles F. Webb
  • Patent number: 9189403
    Abstract: A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, William J. Starke, Jeffrey Stuecheli, Derek E. Williams, Thomas R. Puzak
  • Patent number: 9176876
    Abstract: A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Thomas R. Puzak
  • Patent number: 8826095
    Abstract: A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emma, Wing K. Luk, Thomas R. Puzak, Vijayalakshmi Srinivasan
  • Patent number: 8521999
    Abstract: A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak, Vijayalakshmi Srinivasan
  • Publication number: 20120203973
    Abstract: A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
    Type: Application
    Filed: April 12, 2012
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy L. Guthrie, William J. Starke, Jeffrey Stuecheli, Derek E. Williams, Thomas R. Puzak
  • Patent number: 8131982
    Abstract: A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location, and saving the data in a branch prediction memory, or receiving an unload instruction including the first data location in the first memory area, retrieving data including a branch address and a target address from the branch prediction memory, and saving the data in the first data location.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Allan M. Hartstein, Keith N. Langston, Brian R. Prasky, Thomas R. Puzak, Charles F. Webb
  • Publication number: 20110225401
    Abstract: A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip G. Emma, Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak, Vijayalakshmi Srinivasan
  • Patent number: 8015364
    Abstract: An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Alan G. Gara, Thomas R. Puzak, Valentina Salapura
  • Publication number: 20110161780
    Abstract: A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
    Type: Application
    Filed: March 4, 2011
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip George Emma, Wing K. Luk, Thomas R. Puzak, Vijayalakshmi Srinivasan
  • Publication number: 20110161589
    Abstract: A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Thomas R. Puzak
  • Patent number: 7941728
    Abstract: A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emma, Wing K. Luk, Thomas R. Puzak, Vijayalakshmi Srinivasan
  • Publication number: 20100287358
    Abstract: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 11, 2010
    Applicant: International Business Machines Corporation
    Inventors: Philip G. Emma, Allan M. Hartstein, Keith N. Langston, Brian R. Prasky, Thomas R. Puzak, Charles F. Webb
  • Patent number: 7711904
    Abstract: A system, method and computer program product for executing a cache replacement algorithm. A system includes a computer processor having an instruction processor, a cache and one or more useful indicators. The instruction processor processes instructions in a running program. The cache includes two or more cache levels including a level one (L1) cache level and one or more higher cache levels. Each cache level includes one or more cache lines and has an associated directory having one or more directory entries. A useful indicator is located within one or more of the directory entries and is associated with a particular cache line. The useful indicator is set to provide an indication that the associated cache line contains one or more instructions that are required by the running program and cleared to provide lack of such an indication.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Daniel N. Lynch, Thomas R. Puzak
  • Publication number: 20090313462
    Abstract: A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location data location, and saving the data in a branch prediction memory.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Philip G. Emma, Allan M. Hartstein, Keith N. Langston, Brian R. Prasky, Thomas R. Puzak, Charles F. Webb
  • Patent number: 7493480
    Abstract: A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Klaus J. Getzlaff, Allan M. Hartstein, Thomas Pflueger, Thomas R. Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan
  • Publication number: 20080294850
    Abstract: An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
    Type: Application
    Filed: May 29, 2008
    Publication date: November 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthias A. Blumrich, Alan G. Gara, Thomas R. Puzak, Valentina Salapura
  • Patent number: 7441110
    Abstract: A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: October 21, 2008
    Assignee: International Business Machines Corporation
    Inventors: Thomas R. Puzak, Allan M. Hartstein, Mark Charney, Daniel A. Prener, Peter H. Oden
  • Publication number: 20080235453
    Abstract: A system, method and computer program product for executing a cache replacement algorithm. A system includes a computer processor having an instruction processor, a cache and one or more useful indicators. The instruction processor processes instructions in a running program. The cache includes two or more cache levels including a level one (L1) cache level and one or more higher cache levels. Each cache level includes one or more cache lines and has an associated directory having one or more directory entries. A useful indicator is located within one or more of the directory entries and is associated with a particular cache line. The useful indicator is set to provide an indication that the associated cache line contains one or more instructions that are required by the running program and cleared to provide lack of such an indication.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Applicant: International Business Machines Corporation
    Inventors: Philip G. Emma, Daniel N. Lynch, Thomas R. Puzak
  • Publication number: 20080222358
    Abstract: A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 11, 2008
    Applicant: International Business Machines Corporation
    Inventors: Philip George Emma, Wing K. Luk, Thomas R. Puzak, Vijayalakshmi Srinivasan