Patents by Inventor Thomas R. Sand

Thomas R. Sand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10838816
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christoper J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Publication number: 20190243797
    Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Patent number: 10331605
    Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Patent number: 10296484
    Abstract: The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Patent number: 10275362
    Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
  • Patent number: 10102074
    Abstract: The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Publication number: 20180232317
    Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
  • Patent number: 10025725
    Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: VIctor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
  • Publication number: 20180113813
    Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.
    Type: Application
    Filed: June 26, 2017
    Publication date: April 26, 2018
    Inventors: VIctor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
  • Publication number: 20180081761
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christoper J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Publication number: 20180060266
    Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Patent number: 9891998
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christopher J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Patent number: 9710395
    Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vlctor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
  • Patent number: 9697156
    Abstract: A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Curtis S. Eide, Christopher J. Engel, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand, William A. Thompson
  • Patent number: 9697167
    Abstract: A method, system and computer program product are provided for implementing health check for optical cable attached Peripheral Component Interconnect Express (PCIE) enclosures in a computer system. System firmware is provided for implementing health check functions. One or more optical cables are connected between a host bridge and a PCIE enclosure. A PCIE link to the PCIE enclosure is reset responsive to a predefined event. After a set delay, a PCIE link health check is performed verifying PCIE link width and speed.
    Type: Grant
    Filed: March 19, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christopher J. Engel, Kaveh Naderi, Harald Pross, Thomas R. Sand
  • Patent number: 9697155
    Abstract: A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Curtis S. Eide, Christopher J. Engel, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand, William A. Thompson
  • Patent number: 9697166
    Abstract: A method, system and computer program product are provided for implementing health check for optical cable attached Peripheral Component Interconnect Express (PCIE) enclosures in a computer system. System firmware is provided for implementing health check functions. One or more optical cables are connected between a host bridge and a PCIE enclosure. A PCIE link to the PCIE enclosure is reset responsive to a predefined event. After a set delay, a PCIE link health check is performed verifying PCIE link width and speed.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christopher J. Engel, Kaveh Naderi, Harald Pross, Thomas R. Sand
  • Publication number: 20170154008
    Abstract: The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Publication number: 20170154000
    Abstract: The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each adapter and controls an initial allocation of lanes to each detected adapter for maximizing adapter functionality. After the initial allocation and in response to performance evaluation, the module dynamically switches lanes from the among the adapters, including allocation of available lane, upshifting lane allocation to one or more adapters, and/or downshifting lane allocation to one or more adapters.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
  • Publication number: 20170153989
    Abstract: The embodiments relate to dynamically allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled, which includes the module controlling an allocation of the lanes to adapters present at boot-time. The allocation is dynamic and functions to maximize lane allocation and functionality for the detected adapters.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand