Patents by Inventor Thomas R. Seeman
Thomas R. Seeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130157639Abstract: Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.Type: ApplicationFiled: February 2, 2012Publication date: June 20, 2013Applicant: SRC Computers, LLCInventors: Jon M. Huppenthal, Thomas R. Seeman, Jeffrey Hammes, D. James Guzy
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Publication number: 20120117318Abstract: A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.Type: ApplicationFiled: November 1, 2011Publication date: May 10, 2012Applicant: SRC Computers, Inc.Inventors: Lee A. Burton, Thomas R. Seeman, Jon M. Huppenthal
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Patent number: 7565461Abstract: A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.Type: GrantFiled: August 15, 2005Date of Patent: July 21, 2009Assignee: SRC Computers, Inc.Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 7421524Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.Type: GrantFiled: November 23, 2004Date of Patent: September 2, 2008Assignee: SRC Computers, Inc.Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 7373440Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.Type: GrantFiled: August 17, 2001Date of Patent: May 13, 2008Assignee: SRC Computers, Inc.Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 7197575Abstract: A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.Type: GrantFiled: January 10, 2003Date of Patent: March 27, 2007Assignee: SRC Computers, Inc.Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 7003593Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.Type: GrantFiled: October 29, 2002Date of Patent: February 21, 2006Assignee: SRC Computers, Inc.Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Publication number: 20030061432Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.Type: ApplicationFiled: October 29, 2002Publication date: March 27, 2003Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 6449677Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.Type: GrantFiled: March 11, 1999Date of Patent: September 10, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Sompong Paul Olarig, Thomas R. Seeman, Kenneth Jansen, Dwight D. Riley
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Publication number: 20020019926Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.Type: ApplicationFiled: August 17, 2001Publication date: February 14, 2002Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
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Patent number: 6148359Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.Type: GrantFiled: November 5, 1998Date of Patent: November 14, 2000Assignee: Compaq Computer CorporationInventors: Bassam Elkhoury, Christopher J. Pettey, Dwight Riley, Thomas R. Seeman, Brian S. Hausauer
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Patent number: 6098134Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.Type: GrantFiled: December 31, 1996Date of Patent: August 1, 2000Assignee: Compaq Computer Corp.Inventors: Peter Michels, Christopher J. Pettey, Thomas R. Seeman, Brian S. Hausauer
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Patent number: 6085274Abstract: A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.Type: GrantFiled: March 2, 1999Date of Patent: July 4, 2000Assignee: Compaq Computer CorporationInventor: Thomas R. Seeman
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Patent number: 5881253Abstract: A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.Type: GrantFiled: December 31, 1996Date of Patent: March 9, 1999Assignee: Compaq Computer CorporationInventor: Thomas R. Seeman
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Patent number: 5870567Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.Type: GrantFiled: December 31, 1996Date of Patent: February 9, 1999Assignee: Compaq Computer CorporationInventors: Brian S. Hausauer, Christopher J. Pettey, Thomas R. Seeman
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Patent number: 5835741Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.Type: GrantFiled: December 31, 1996Date of Patent: November 10, 1998Assignee: Compaq Computer CorporationInventors: Bassam Elkhoury, Christopher J. Pettey, Dwight Riley, Thomas R. Seeman, Brian S. Hausauer
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Patent number: 5832243Abstract: A computer system using posted memory write buffers in a bridge can implement the stop clock acknowledge special cycle without faulty operation. The stop clock acknowledge transaction is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted stop clock acknowledge transaction. In this way, bridges having both posted write buffers and the stop clock special cycle may be utilized in efficient joint operation.Type: GrantFiled: December 31, 1996Date of Patent: November 3, 1998Assignee: Compaq Computer CorporationInventor: Thomas R. Seeman
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Patent number: 5659789Abstract: The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.Type: GrantFiled: December 15, 1995Date of Patent: August 19, 1997Assignee: Compaq Computer CorporationInventors: Brian S. Hausauer, Thomas R. Seeman
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Patent number: RE37980Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.Type: GrantFiled: November 3, 2000Date of Patent: February 4, 2003Assignee: Compaq Computer CorporationInventors: Bassam Elkhoury, Christopher J. Pettey, Dwight Riley, Thomas R. Seeman, Brian S. Hausauer