Abstract: A receiver for recovering serial digital data, such as teletext, achieves an effective sampling rate which is a multiple of the local receiver clock frequency by passing the data signal through a multi-tap delay line. The delay line outputs are supplied to a register, and the register output which yields the lowest bit error rate is determined and used as the data sampling point. The optimum sampling point is determined by first ascertaining a nominal sampling point from the signal preamble and then programmatically incrementing through the available sampling points (register outputs) until there is no improvement in bit error rate.

Abstract: A masker unit in a data processor employed to achieve programmable data path widths for the buses within the processor. A mask generator is provided to partially decode a mask amount from the currently executed control instruction and masking logic is provided with additional decoding logic to complete the mask amount decode.

Abstract: A processor is disclosed having two levels of subinstructions, with the processor data bus being selectable as either a 16 bit or 32 bit wide bus under nanoprogram control.

Abstract: A receiver for recovering serial digital data, such as teletext, achieves an effective sampling rate which is a multiple of the local receiver clock frequency by passing the data signal through a multitap delay line. The delay line outputs are supplied to a register, and the register output which yields the lowest bit error rate is determined and used as the data sampling point. The optimum sampling point is determined by first ascertaining a nominal sampling point from the signal preamble and then programmatically incrementing through the available sampling points (register outputs) until there is no improvement in bit error rate.

Abstract: A processor has two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower level instructions that are desired to be used being supplied by the code stream from the upper level memory.

Abstract: A loosely coupled parallel network simulator has been described which employs a time multiplex bus to which a plurality of processing sites are coupled with each processing site being assigned one or more particular time slots during the bus cycle. Each processing site contains a sequencing RAM or control store which determines that clock time during the bus cycle that the processing site is to be given access for either transmission or reception of data segments.

Abstract: Disclosed is a programmable multiplexer integrated on a semiconductor chip comprised of a plurality of fixed multiplexer circuits, each of which includes a plurality of data inputs, a plurality of control inputs, and an output for passing a signal from any one of the data inputs to the output in a fixed predetermined fashion in response to encoded signals on the control inputs; and associated with each of the fixed multiplexer circuits is a programmable memory for generating the encoded control signals by performing respective programmable transformation of one common address that is sent to all of the memories.

Abstract: A circuit for accurately reconstructing the timing information encoded within digital waveforms of the double frequency class includes facilities for restoring the circuit to proper synchronization at start up time or after a burst of noise on an incoming waveform. The circuit first generates three delayed versions of the incoming double frequency waveform. Transitions in the incoming waveform are detected by comparing the incoming waveform with the first delayed waveform and simultaneously comparing the second and third delayed waveforms, the generated transition-event waveforms being identical but out of phase by one half of the bit cell time of the incoming waveform. The two generated transition waveforms are used to form a composite clock which is then used to toggle the state of a D-type flip-flop at one half bit cell intervals.

Abstract: A circuit arrangement for extracting clocking signals from double frequency encoded transition-event waveforms. The incoming waveform is fed directly into a digital delay line which generates three versions of the incoming waveform, each delayed by 1/4, 1/2 and 3/4 of the incoming waveform's bit cell time, respectively. Transitions in the incoming waveform are detected by comparing the output of the first delay line tap with the incoming waveform and simultaneously comparing the outputs of the second and third delay line taps, thus generating first and second transition waveforms that are identical but out of phase by one-half bit cell. The two generated transition waveforms are used to form a composite clock which is then used to toggle a flip-flop at one-half bit cell intervals.

Abstract: Primary and back-up closed loop unidirectional transmission lines transmit self-clocking data streams and null data, respectively, in opposite directions to a plurality of loop interface units (LIUs) connected to the primary and back-up lines. To protect against failure of the entire system due to a break in the primary and/or back-up lines or failure of one of the loop interface units, each loop interface unit can detect a signal loss on the primary or back-up transmission line and wrap signal flow to bypass the detected fault. After wrapping around a detected fault, an LIU then creates a failure on the non-failing line causing an analogous wraparound in the LIU on the other side of the actual failure. After error recovery, there is then a complete loop connecting all non-failing loop interface units, although it is twice as long as before the signal loss was detected.