Patents by Inventor Thomas Ribarich

Thomas Ribarich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12640730
    Abstract: A circuit is disclosed. The circuit includes a gallium nitride (GaN) switch having a gate terminal, a drain terminal and a source terminal, a driver circuit having an output terminal coupled to the gate terminal, where the driver circuit is arranged to generate an output voltage at the output terminal such that: the output voltage is at a first voltage when a voltage at the drain terminal is below a predetermined voltage; the output voltage is at a second voltage when 1) the voltage at the drain terminal is above the predetermined voltage and 2) a time period during which the output voltage is at the second voltage is less than a predetermined time. In one aspect, the second voltage is greater than the first voltage.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: May 26, 2026
    Assignee: Navitas Semiconductor Limited
    Inventors: Nabil Akel, Jason Zhang, Victor Sinow, Thomas Ribarich
  • Publication number: 20260031807
    Abstract: Systems and methods for a GaN-based motor drive circuit using synchronous rectification is disclosed. In one aspect, a method of operating a motor drive circuit includes providing a half-bridge circuit including a high-side GaN switch and a low-side GaN switch coupled in series at an output node, providing a motor coupled to the output node, turning on the high-side GaN switch such that a first current flows through the motor, turning off the high-side GaN switch, turning on the low-side GaN switch when a voltage at the output node drops below a predetermined threshold voltage, sensing, using a sense device coupled to the low-side GaN switch, a magnitude of a second current that flows through the low-side GaN switch, and turning off the low-side GaN switch when the magnitude of the second current drops below a predetermined threshold current.
    Type: Application
    Filed: October 3, 2025
    Publication date: January 29, 2026
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh SHARMA, Thomas RIBARICH, Matteo UCCELLI, Victor SINOW
  • Patent number: 12438535
    Abstract: Systems and methods for a GaN-based motor drive circuit using synchronous rectification is disclosed. In one aspect, a method of operating a motor drive circuit includes providing a half-bridge circuit including a high-side GaN switch and a low-side GaN switch coupled in series at an output node, providing a motor coupled to the output node, turning on the high-side GaN switch such that a first current flows through the motor, turning off the high-side GaN switch, turning on the low-side GaN switch when a voltage at the output node drops below a predetermined threshold voltage, sensing, using a sense device coupled to the low-side GaN switch, a magnitude of a second current that flows through the low-side GaN switch, and turning off the low-side GaN switch when the magnitude of the second current drops below a predetermined threshold current.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: October 7, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Thomas Ribarich, Matteo Uccelli, Victor Sinow
  • Patent number: 12395093
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: August 19, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 12334421
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: June 17, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Publication number: 20240405764
    Abstract: A circuit is disclosed. The circuit includes a gallium nitride (GaN) switch having a gate terminal, a drain terminal and a source terminal, a driver circuit having an output terminal coupled to the gate terminal, where the driver circuit is arranged to generate an output voltage at the output terminal such that: the output voltage is at a first voltage when a voltage at the drain terminal is below a predetermined voltage; the output voltage is at a second voltage when 1) the voltage at the drain terminal is above the predetermined voltage and 2) a time period during which the output voltage is at the second voltage is less than a predetermined time. In one aspect, the second voltage is greater than the first voltage.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 5, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Nabil Akel, Jason Zhang, Victor Sinow, Thomas Ribarich
  • Publication number: 20230387067
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 30, 2023
    Applicant: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Publication number: 20230308091
    Abstract: Systems and methods for a GaN-based motor drive circuit using synchronous rectification is disclosed. In one aspect, a method of operating a motor drive circuit includes providing a half-bridge circuit including a high-side GaN switch and a low-side GaN switch coupled in series at an output node, providing a motor coupled to the output node, turning on the high-side GaN switch such that a first current flows through the motor, turning off the high-side GaN switch, turning on the low-side GaN switch when a voltage at the output node drops below a predetermined threshold voltage, sensing, using a sense device coupled to the low-side GaN switch, a magnitude of a second current that flows through the low-side GaN switch, and turning off the low-side GaN switch when the magnitude of the second current drops below a predetermined threshold current.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 28, 2023
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Thomas Ribarich, Matteo Uccelli, Victor Sinow
  • Patent number: 11715720
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 1, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 11594970
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: February 28, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel M. Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Publication number: 20220231606
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 21, 2022
    Applicant: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel M. Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Publication number: 20220102251
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 31, 2022
    Applicant: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Publication number: 20220084978
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Application
    Filed: February 5, 2021
    Publication date: March 17, 2022
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 11251709
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 15, 2022
    Assignee: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 11145579
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: October 12, 2021
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 10931200
    Abstract: A current detecting GaN FET is disclosed. The current detecting GaN FET includes a first GaN switch having a first gate, a first drain, a first source, and a first field plate. The current detecting GaN FET also includes a second GaN switch having a second gate, a second drain, a second source, and a second field plate. The current detecting GaN FET also includes a resistor. The first and second gates are electrically connected, the first and second drains are electrically connected, and the resistor is connected between the first and second sources.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: February 23, 2021
    Assignee: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 10833589
    Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Thomas Ribarich, Victor Sinow, Daniel Marvin Kinzer
  • Publication number: 20200328682
    Abstract: A current detecting GaN FET is disclosed. The current detecting GaN FET includes a first GaN switch having a first gate, a first drain, a first source, and a first field plate. The current detecting GaN FET also includes a second GaN switch having a second gate, a second drain, a second source, and a second field plate. The current detecting GaN FET also includes a resistor. The first and second gates are electrically connected, the first and second drains are electrically connected, and the resistor is connected between the first and second sources.
    Type: Application
    Filed: May 1, 2020
    Publication date: October 15, 2020
    Applicant: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 10778219
    Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 15, 2020
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Publication number: 20200220463
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow