Patents by Inventor Thomas Richard Miller
Thomas Richard Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7378227Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.Type: GrantFiled: October 20, 2004Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
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Patent number: 6815126Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.Type: GrantFiled: April 9, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
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Publication number: 20030188886Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.Type: ApplicationFiled: April 9, 2002Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
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Structure for high speed printed wiring boards with multiple differential impedance-controlled layer
Patent number: 6570102Abstract: A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.Type: GrantFiled: June 11, 2001Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Thomas Richard Miller, Konstantinos I. Papathomas, Brian Eugene Curcio, Joseph J. Sniezek -
Patent number: 6544584Abstract: A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g.Type: GrantFiled: March 7, 1997Date of Patent: April 8, 2003Assignee: International Business Machines CorporationInventors: Edward Lee Arrington, John Christopher Camp, Robert Jeffrey Day, Edmond Otto Fey, Curtis Michael Gunther, Thomas Richard Miller
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Patent number: 6436803Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension.Type: GrantFiled: April 23, 2001Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Structure for high speed printed wiring boards with multiple differential impedance-controlled layer
Publication number: 20020007966Abstract: A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.Type: ApplicationFiled: June 11, 2001Publication date: January 24, 2002Applicant: International Business Machines CorporationInventors: Thomas Richard Miller, Konstantinos I. Papathomas, Brian Eugene Curcio, Joseph J. Sniezek -
Publication number: 20010033889Abstract: The present invention provides a method for electrolessly depositing metal onto a substrate, comprising: exposing a surface of the substrate to a first solution including a surfactant; and exposing the surface, having residual surfactant from the first solution thereon, to a second solution including ions of an electroconductive metal element for plating the surface with the electroconductive metal while exposed to the second solution; wherein the surface is exposed to the first solution immediately prior to exposing the surface to the second solution.Type: ApplicationFiled: April 23, 2001Publication date: October 25, 2001Inventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Patent number: 6268016Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension.Type: GrantFiled: June 28, 1996Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Patent number: 6265075Abstract: A circuitized semiconductor structure comprising a layer of dielectric material, a catalyst seed layer above the layer of dielectric material, a layer of photoimageable dielectric material on the catalyst seed layer and having openings therein, a nickel layer in the openings and a layer of copper in the openings above the nickel layer and being coplanar with the top of the layer of dielectric material is provided, along with a method for its fabrication.Type: GrantFiled: July 20, 1999Date of Patent: July 24, 2001Assignee: International Business Machines CorporationInventors: David Anton Klueppel, Voya R. Markovich, Thomas Richard Miller, Timothy L. Wells, William Earl Wilson
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Patent number: 6225028Abstract: A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.Type: GrantFiled: January 13, 2000Date of Patent: May 1, 2001Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Thomas Richard Miller, Allen Frederick Moring, James Paul Walsh
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Patent number: 6110650Abstract: A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.Type: GrantFiled: March 17, 1998Date of Patent: August 29, 2000Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Thomas Richard Miller, Allen Frederick Moring, James Paul Walsh
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Patent number: 6063481Abstract: A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g.Type: GrantFiled: March 6, 1998Date of Patent: May 16, 2000Assignee: International Business Machines CorporationInventors: Edward Lee Arrington, John Christopher Camp, Robert Jeffrey Day, Edmond Otto Fey, Curtis Michael Gunther, Thomas Richard Miller
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Patent number: 5997997Abstract: The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.Type: GrantFiled: June 13, 1997Date of Patent: December 7, 1999Assignee: International Business Machines Corp.Inventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Luis Jesus Matienzo, Thomas Richard Miller, Voya Rista Markovich
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Patent number: 5953594Abstract: An improved method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed, and at least one added layer of metallization is then applied to assure an entirely conductive opening between the member's opposing surfaces. The temporary support assures effective support for the dry film photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.Type: GrantFiled: March 20, 1997Date of Patent: September 14, 1999Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Thomas Richard Miller, Allen Frederick Moring, James Paul Walsh
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Patent number: 5935652Abstract: The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.Type: GrantFiled: March 23, 1998Date of Patent: August 10, 1999Assignee: International Business Machines Corp.Inventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Luis Jesus Matienzo, Thomas Richard Miller, Voya Rista Markovich