Abstract: A self-clocking data entry unit system including a plurality of data entry units connected in seris in a loop which is connected at its ends to a controller. Data bits are provided by the controller flowing in one direction through the loop to each of the data entry units, and the data entry units supplant these data bits with new data bits which flow in the same direction through the loop back to the controller. Control bits are interspersed with the data bits, and each of the data bits has an accompanying tag bit that acts as a controlling bit but is of a different type than the first mentioned control bits so that there is a controlling bit of one type or another for each of the bit positions flowing through the loop for controlling the operation of the data entry units and maintaining their operation synchronized with the micro-controller.